Wafer-Level Substrate for Optoelectronic Modules
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Solution Overview
Problem
The existing methods for fabricating integrated modules with bench substrates and optoelectronic devices face challenges in achieving desired optical performance, particularly in focusing the output from optoelectronic emitters, and there is a need for improvements in the design and fabrication process.
Innovation Solution
The method involves bonding first and second wafer-level substrates together to form a substrate assembly, with exposed electrically conductive elements, and processing the second substrate to create individual elements with controlled thicknesses and electrical connections for mounting optoelectronic devices, which includes forming conductive elements extending through the substrate and using a ball grid array for interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If individual units are fabricated traditionally, then each unit can be assembled separately, but achieving desired optical performance and focusing of output from optoelectronic emitters becomes difficult
Solution Approach 1:
The patent merges multiple fabrication operations into a single wafer-level processing step. Multiple substrate elements are processed simultaneously on a wafer scale, with conductive elements formed through the substrate in one batch operation. This combining of operations achieves precise optical alignment and focusing performance while reducing the overall fabrication process complexity compared to traditional individual unit assembly.
2Productivity
If wafer-level processing is used, then productivity and consistency are improved, but the complexity of processing multiple substrates together increases
Solution Approach 1:
The patent segments the wafer into multiple individual substrate elements that are processed simultaneously but can be separated into discrete functional units. Each element contains its own conductive pathways and optoelectronic device mounting area. This segmentation allows high-volume parallel processing for improved productivity while maintaining the ability to create consistent, standardized components with controlled thicknesses and electrical connections.
Solution Approach 2:
The wafer-level processing platform serves multiple functions: it simultaneously forms conductive elements, creates mechanical support structures, defines individual substrate elements with controlled thicknesses, and prepares mounting surfaces for optoelectronic devices. This multi-functionality in a single processing system improves productivity while managing complexity through integration rather than separate specialized processes.
3Manufacturing precision
If substrate thickness is controlled individually, then optical focusing performance is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent controls substrate thickness as a defined parameter during the wafer-level processing stage. By establishing thickness specifications early in the manufacturing process and maintaining them through subsequent operations, the system achieves precise thickness control for optimal optical focusing performance. This parameter management approach simplifies manufacturing compared to individual post-processing adjustments, as thickness is controlled proactively rather than requiring complex corrective operations later.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-performance integrated modules with improved optical focusing capabilities and mechanical support, suitable for use in consumer electronics, by allowing for precise electrical and optical integration of optoelectronic devices.
Implementation Method 1
bonding first and second wafer-level substrates together to form a substrate assembly
Data Source
AI summary
A method of fabricating a plurality of components using wafer-level processing can include bonding first and second wafer-level substrates together to form a substrate assembly, such that first surfaces of the first and second substrates confront one another, the first substrate having first electrically conductive elements exposed at the first surface thereof, forming second electrically conductive elements contacting the first conductive elements, and processing the second substrate into individual substrate elements. The second conductive elements can extend through a thickness of the first substrate and can be exposed at a second surface thereof opposite the first surface. The processing can include trimming material to produce the substrate elements at least some of which have respective different controlled thicknesses between first surfaces adjacent the first substrate and second surfaces opposite therefrom.