Wafer-Level Test Access Mechanism for Parallel IC Die Testing
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Solution Overview
Problem
Current methods for testing integrated circuit dies on wafers are time-consuming and costly, often requiring individual probing or the inclusion of wireless transceivers in all dies, which increases costs and does not efficiently reduce wafer level test time.
Innovation Solution
A wafer-level test access mechanism (TAM) transceiver circuitry is used to provide input test data in parallel to multiple interconnected pipeline dies, allowing simultaneous testing and comparison of responses, with match/mismatch bits indicating defective dies, and optional wireless communication for reduced test time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual probing is used to test each die, then testing completeness is improved, but manufacturing time and cost increase dramatically
Solution Approach 1:
The wafer is divided into multiple test groups, with each group containing multiple dies that can be tested simultaneously. This segmentation allows parallel testing while maintaining comprehensive coverage, resolving the contradiction between testing completeness and manufacturing time by testing multiple dies at once rather than one at a time
Solution Approach 2:
Multiple dies are combined into test groups that share common test resources (probes, test patterns, and evaluation logic). By merging the testing of multiple dies into a single coordinated operation, the system achieves comprehensive testing without the time penalty of sequential individual testing
2Productivity
If wireless transceivers are included in all dies for contactless testing, then testing speed is improved, but die cost increases
Solution Approach 1:
The wireless transceiver functionality is extracted from individual dies and implemented as external test equipment. This allows contactless testing to proceed at high speed without adding complex and costly wireless circuitry to each die, thereby improving testing speed while controlling die cost
Solution Approach 2:
An external wireless communication system serves as an intermediary between the test equipment and the dies. This mediator enables contactless data transmission for testing without requiring wireless transceivers to be integrated into each die, achieving fast testing while avoiding increased die complexity and cost
3Productivity
If multi-site testing with simultaneous stimulus broadcasting is used, then wafer level test time is reduced, but test system complexity increases
Solution Approach 1:
The multi-site testing system is segmented into modular test groups, where each group can be independently configured and tested. This modular approach reduces test system complexity by breaking down the complex simultaneous testing of all dies into manageable groups, while still achieving reduced wafer level test time through parallel testing
Solution Approach 2:
Instead of requiring all dies to be tested simultaneously with full stimulus broadcasting to every die, the system applies partial action by testing subsets of dies in groups. This reduces the complexity burden of full simultaneous multi-site testing while still achieving significant reductions in wafer level test time through parallel processing of multiple dies
Data Source
AI summary
A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines. When on the wafer, the dies in a pipeline are interconnected with pipeline die test interconnection paths that provide pipeline test information interconnection among the plurality of dies in the pipeline.