Wafer-Level 3D Die Stacking for Varied Die Hybrid Bonding
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Solution Overview
Problem
Conventional microelectronic packaging technologies face inefficiencies in stacking and interconnecting dies of varying sizes and technologies, leading to reduced yield and increased costs due to the need for identical chip dimensions and restrictive material usage.
Innovation Solution
The implementation of direct hybrid bonding techniques at the wafer level allows for the mixing and matching of dies with different physical sizes, form factors, and foundry nodes, using a molding material with matched thermal expansion coefficients to create high-density signal connections and vertical stacks within a single micropackage, eliminating the need for ball grid arrays and standard interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional packaging technologies use identical chip dimensions and standard interfaces, then manufacturing process is simplified, but device complexity and cost increase due to inability to use variegated dies
Solution Approach 1:
The patent segments the packaging process into distinct stages: wafer-level preparation, die stacking, and post-packaging processing. This allows different sized dies to be processed independently and then combined, enabling variegated die usage without requiring complete process redesign.
Solution Approach 2:
The patent transitions from conventional 2D planar packaging to 3D vertical stacking. By arranging dies in multiple layers vertically rather than horizontally, the system can accommodate dies of varying footprints and technologies in the same package volume, significantly improving adaptability.
2Volume of moving object
If wafer level packaging is used to create compact packages, then package size is reduced, but manufacturing yield decreases due to restrictive material usage and identical dimension requirements
Solution Approach 1:
The patent changes the key parameter from requiring identical die dimensions to accepting varied die dimensions. By modifying the dimensional constraints and using thermal expansion matched materials, the process achieves high yield while maintaining compact package volumes through vertical stacking of non-uniform dies.
3Use of energy by moving object
If conventional packaging processes are used, then manufacturing is simpler, but power consumption increases due to less efficient thermal management and routing
Solution Approach 1:
By moving from 2D planar routing to 3D vertical interconnection, the patent achieves ultra-high density routing with shorter signal paths. This dimensional transition improves power efficiency through reduced resistive losses while the wafer-level process maintains manufacturing simplicity.
Solution Approach 2:
The patent uses composite materials with matched thermal expansion coefficients to enable efficient thermal management in the stacked structure. These materials facilitate heat dissipation pathways that reduce power consumption while maintaining ease of manufacture through standard wafer-level processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-yield production of compact microelectronics packages with increased computing power and reduced power consumption by allowing the use of variegated dies in mixed technology stacks, providing ultra-high density routing and efficient thermal management.
Implementation Method 1
using a molding material with matched thermal expansion coefficients
Data Source
AI summary
Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.