Wafer-Level MEMS Package Cavity for Fragile Piezoelectric Substrates
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Solution Overview
Problem
Handling and fabrication of fragile piezoelectric substrates used in MEMS devices, such as SAW and BAW filters, are challenging due to their fragility, which complicates the integration of these devices into chip-scale packages.
Innovation Solution
A wafer-level chip-scale package design that includes a polymeric body with a conductive via and a piezoelectric substrate directly bonded using transient liquid phase or solder bonds, along with a seal ring and dielectric layers to create a hermetically sealed cavity, allowing for the integration of interdigital electrodes and passive devices like inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If piezoelectric substrates are used in MEMS devices, then device functionality is achieved, but handling and fabrication become challenging due to fragility
Solution Approach 1:
The patent applies preliminary action by forming the piezoelectric substrate and MEMS device structures on a carrier wafer before final packaging. The carrier wafer provides mechanical support during fabrication, and the package body is formed around the substrate in advance, creating a protective structure before the substrate is transferred to its final position. This preliminary structuring reduces handling challenges during manufacturing.
Solution Approach 2:
The patent uses the carrier wafer as an intermediary during the fabrication process. The carrier wafer temporarily holds the fragile piezoelectric substrate, allowing manipulation and processing without directly handling the fragile substrate itself. The package body also acts as an intermediary protective structure that is formed around the substrate before final assembly, mediating between the fragile substrate and external handling forces.
2Productivity
If piezoelectric substrates are directly handled during fabrication, then fabrication progress is made, but substrate damage risk increases
Solution Approach 1:
The package body is formed on the carrier wafer before the piezoelectric substrate is transferred to it. This preliminary formation of the protective package structure allows subsequent substrate placement and sealing operations to proceed without risking substrate damage, as the protective enclosure is already in place.
Solution Approach 2:
The package body acts as a beforehand cushioning structure that is formed around the piezoelectric substrate before final assembly. This protective enclosure cushions the fragile substrate from mechanical stresses and damage risks during subsequent handling and operation, allowing fabrication progress while maintaining substrate integrity.
3Reliability
If a hermetically sealed cavity is created, then MEMS device protection is improved, but package complexity increases
Solution Approach 1:
The patent merges multiple functions into the package body structure. The package body simultaneously provides mechanical support, hermetic sealing, and electrical isolation functions. By combining these functions into a single integrated structure formed on the carrier wafer, the patent achieves effective MEMS protection while minimizing the addition of separate complex components.
Solution Approach 2:
The package body is designed with multi-functionality, serving as both the protective enclosure and the sealing structure. The same structure that provides mechanical protection also creates the hermetic seal when bonded to the carrier wafer, eliminating the need for separate sealing components and reducing overall package complexity despite providing comprehensive protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the handling and integration of MEMS devices by providing a robust and hermetically sealed package that improves the reliability and performance of MEMS devices, particularly in RF applications, by reducing the fragility issues associated with piezoelectric substrates.
Implementation Method 1
A piezoelectric substrate is directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond
Implementation Method 2
A piezoelectric substrate is directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond
Data Source
AI summary
A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.