Wafer-Level Multi-Die Layout Using Inter-Die Space
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Solution Overview
Problem
Conventional semiconductor fabrication methods leave significant wasted space between dies on a wafer, which could be utilized to enhance functionality or versatility of the fabricated dies.
Innovation Solution
Implementing interconnected IC dies with dual seal rings and conductive elements to utilize the otherwise wasted space between dies, forming electrical connections and incorporating additional structures like dummy elements, test structures, and patterns to improve chip area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If conventional fabrication methods are used to form IC dies on a wafer, then the dies can be manufactured with standard processes, but significant wasted space remains between the dies
Solution Approach 1:
The patent converts the previously wasted space between dies into beneficial functional areas by forming additional circuit structures, test structures, and interconnect elements in these gap regions. This transforms the harmful waste space into a resource that enhances the overall functionality and versatility of the die assembly.
Solution Approach 2:
The patent merges the functional areas of individual dies with the previously wasted gap regions by forming continuous circuit structures that extend across die boundaries. This combining of spaces creates integrated multi-die structures where the gaps between dies become part of the functional circuitry.
2Adaptability or versatility
If more space is utilized between dies by adding additional structures, then chip area utilization and functionality are enhanced, but the device complexity increases
Solution Approach 1:
The patent implements multi-functional structures in the gap regions that serve multiple purposes: additional circuit functionality, test structures for validation, interconnect elements for die-to-die communication, and space utilization to reduce waste. This multi-functionality approach enhances versatility without proportionally increasing complexity.
3Productivity
If conventional fabrication methods are used, then manufacturing processes are simple and well-established, but production efficiency and cost-effectiveness are limited due to wasted space
Solution Approach 1:
The patent combines the fabrication of individual dies with the formation of inter-die structures in a single integrated process flow. By merging these previously separate steps into one unified fabrication sequence, the patent improves production efficiency and reduces manufacturing costs while eliminating wasted space.
Solution Approach 2:
The patent performs preliminary actions by forming interconnect structures and additional circuit elements in the gap regions during the same fabrication process as the dies themselves, rather than requiring subsequent separate processing steps. This preliminary integration improves productivity and reduces overall manufacturing complexity.
Data Source
AI summary
An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.