Semiconductor Wafer Nanotopography Evaluation via Capacitive Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for evaluating nanotopography of semiconductor wafers during intermediate steps, such as slicing and lapping, are inaccurate due to process strain, making it difficult to precisely detect waviness and control subsequent manufacturing steps.
Innovation Solution
A semiconductor-wafer evaluation method using a capacitive shape measurement device to measure warp data before the mirror-polishing step, with a specified sampling range and fitting function to eliminate process strain effects, allowing for precise evaluation of nanotopography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If optical measurement instruments are used to measure nanotopography, then measurement can be performed on mirror-polished wafers, but measurement is inaccurate or unreliable on wafers with low reflectance surfaces
Solution Approach 1:
The patent replaces optical measurement instruments with a capacitive shape measurement device. The capacitive device measures surface shape by detecting capacitance changes between a probe and the wafer surface, eliminating dependence on surface reflectance. This allows accurate nanotopography measurement at intermediate steps including slicing, lapping, and grinding where surfaces lack mirror finish.
2Ease of operation
If conventional optical measurement methods are used, then measurement is simple, but process strain causes inaccurate warp data that does not reflect actual waviness
Solution Approach 1:
The patent introduces a preliminary data processing step where warp data is fitted with appropriate functions to eliminate the effects of process strain before analyzing waviness. This preliminary action separates the strain component from the actual surface shape, allowing accurate waviness detection from capacitive measurement data without requiring physical removal of strain through etching.
3Manufacturing precision
If multiple intermediate processing steps are added to reduce waviness, then nanotopography improves, but manufacturing complexity and time increase
Solution Approach 1:
The patent implements a feedback mechanism where capacitive shape measurement is performed at intermediate steps to monitor nanotopography in real-time. The measured data, after eliminating strain effects through fitting, provides feedback to control subsequent processing steps. This allows optimization of the manufacturing process to achieve required flatness with minimal necessary steps, avoiding unnecessary additional processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-precision evaluation of nanotopography before the mirror-polishing step, improving the correlation with post-polishing results and enabling efficient control of manufacturing steps, reducing defects and increasing yield.
Implementation Method 1
measuring warp data of displacement of a surface of a semiconductor wafer with a capacitive shape measurement device
Data Source
AI summary
A semiconductor-wafer evaluation method includes: before the mirror-polishing step, measuring warp data of displacement of the surface of the semiconductor wafer with a capacitive shape measurement device; setting a prescribed width of an outer circumferential portion of the semiconductor wafer as a sampling range; performing fitting of the warp data within the sampling range with a fitting function in a predetermined fitting range; calculating a difference (Range) between a maximum and a minimum of the warp data after the fitting within the sampling range; and, after the mirror-polishing step, evaluating the nanotopography of the surface of the semiconductor wafer on the basis of the calculated difference (Range).