Semiconductor Wafer Notch Polishing for Surface Roughness Control
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Solution Overview
Problem
The mirror-surface chamfering step in semiconductor wafer manufacturing often results in deteriorated surface roughness of the wafer notch portion due to high polishing rates, which compromises the quality of the semiconductor wafer.
Innovation Solution
A method involving a first mirror-surface chamfering process before the double-side polishing step and a second mirror-surface chamfering process after, with a reduced polishing rate in the second process, to specifically target and improve the surface roughness of the wafer notch portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large polishing rate is used in the mirror-surface chamfering step to maintain productivity, then productivity is improved, but surface roughness of the wafer notch portion deteriorates
Solution Approach 1:
The mirror-surface chamfering process is divided into multiple sequential polishing steps with different polishing rates. The first polishing step uses a relatively large polishing rate for initial material removal, while the second polishing step uses a smaller polishing rate to achieve the final surface quality, thereby resolving the contradiction between productivity and surface roughness
Solution Approach 2:
The polishing rate parameter is changed between different polishing steps. By reducing the polishing rate in the second polishing step compared to the first step, the invention achieves both sufficient material removal and improved surface roughness, resolving the contradiction between productivity and manufacturing precision
2Manufacturing precision
If the polishing time for the wafer notch portion is extended to improve surface roughness, then surface roughness is improved, but residence time in the apparatus increases and productivity deteriorates
Solution Approach 1:
The polishing rate parameter is optimized differently for different steps: a larger polishing rate in the first step enables faster material removal, while a smaller polishing rate in the second step achieves the required surface roughness. This parameter differentiation allows the process to meet quality requirements without excessively extending the total polishing time
Solution Approach 2:
The first polishing step performs preliminary material removal at a higher rate before the second polishing step refines the surface. This preliminary action reduces the total material that needs to be removed at the slower rate in the second step, thereby reducing the overall residence time while achieving the required surface quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively inhibits the deterioration of surface roughness while maintaining productivity, resulting in a semiconductor wafer with improved notch roughness and quality.
Implementation Method 1
a mirror-surface chamfering step of polishing the chamfered portion to form a mirror surface
Implementation Method 2
Roughness after the process depends on a type of a polishing cloth, a type of a polishing slurry, a process time
Data Source
AI summary
A method for manufacturing a semiconductor wafer, including: a chamfering step of grinding at least a periphery of a wafer to form a chamfered portion having a wafer edge portion and a wafer notch portion; a double-side polishing step; a mirror-surface chamfering step; and a mirror polishing step, wherein the mirror-surface chamfering step includes: a first mirror-surface chamfering process of polishing the wafer notch portion in the chamfered portion before the double-side polishing step; and a second mirror-surface chamfering process of polishing the wafer notch portion and the wafer edge portion after the double-side polishing step, and a polishing rate of the wafer notch portion in the second mirror-surface chamfering process is smaller than a polishing rate of the wafer notch portion in the first mirror-surface chamfering process.