Wafer-Level Package Seal Ring Layout for Uniform MEMS Bonding
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Solution Overview
Problem
Microelectromechanical systems (MEMS) devices face issues with electrical failures and mechanical damages due to non-uniform bonding techniques, leading to void formation, misalignments, and poor bonding quality, which are exacerbated by the complexity of forming electrical connections.
Innovation Solution
A wafer level package with a sealing structure featuring a seal ring and a bonding layer, where micro-rings within the seal ring confine the bonding material, providing precise gap control and increased process window, and a lateral electrical connection line extending through the seal ring for reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding techniques are used to seal two wafers together, then hermetic sealing is achieved, but non-uniform bonding temperature and force cause void formation and gap dimension variation
Solution Approach 1:
The bonding layer is segmented into multiple discrete bonding islands rather than a continuous layer. Each bonding island is formed by depositing bonding material at specific locations between the first and second wafers, allowing independent control of each bonding region. This segmentation enables uniform bonding across the entire wafer interface despite temperature and force non-uniformities, preventing void formation and gap variation while maintaining hermetic sealing.
2Strength
If eutectic bonding is used to bond substrates, then bonding strength is improved, but excessive squeezing of bonding material out from seal ring area occurs
Solution Approach 1:
The bonding material is distributed as discrete bonding islands rather than a continuous layer. During eutectic bonding, the molten bonding material is confined within these segmented regions, preventing excessive squeezing out from the seal ring area. The segmentation contains the molten material within defined boundaries, reducing material loss while still achieving strong bonding.
Solution Approach 2:
The bonding material is strategically placed only at specific locations where bonding is needed, rather than uniformly across the entire wafer surface. This local placement ensures that bonding material is concentrated where it provides maximum bonding strength, while minimizing the total amount of material that could be squeezed out during the bonding process.
3Ease of manufacture
If conventional bonding techniques are used, then substrates can be bonded, but bonding misalignments occur due to small process window
Solution Approach 1:
The bonding interface is divided into multiple discrete bonding islands rather than requiring uniform bonding across the entire wafer surface. This segmentation relaxes the alignment requirements, as each bonding island can be independently positioned and bonded. The small process window is compensated by the tolerance inherent in segmented bonding, where minor misalignments do not affect the overall bonding quality.
Solution Approach 2:
The bonding material is pre-deposited in the form of bonding islands before the actual bonding process. This preliminary placement of bonding material provides built-in alignment references and tolerance compensation, allowing the wafers to be bonded even with minor misalignments. The pre-formed bonding islands guide the bonding process and reduce sensitivity to alignment errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances bonding quality by controlling the bonding layer's squeezing, reducing voids and misalignments, and providing a reliable electrical connection, thus improving the overall quality of the wafer level package.
Implementation Method 1
at least a portion of the material of the bonding layer is located between the micro-rings... when said material melts during the bonding process
Implementation Method 2
a lateral electrical connection line on a surface of the first substrate, which lateral electrical connection line extends through the seal ring for creating an electrical connection between the device inside the package and an electrical circuit outside the package
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
According to an example aspect of the present invention, there is provided a wafer level package (100) for a device, the package (100) comprising: a first substrate (11) and a second substrate (22), a sealing structure comprising a seal ring (40) and a bonding layer (30) between the first substrate (11) and the second substrate (22), and a lateral electrical connection line (50) on a surface of the first substrate (11), which lateral electrical connection line (50) extends through the seal ring (40) for creating an electrical connection between the device inside the package (100) and an electrical circuit outside the package (100).