Wafer-Level Package Structure for Thermal Stress Reduction
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Solution Overview
Problem
Wafer level packaging techniques face issues with wafer breakage due to thermal expansion differences in materials, leading to mechanical stress and increased scrap rates, especially when using anisotropic crystal cut wafers for micro-acoustic devices.
Innovation Solution
A wafer level package design featuring a functional wafer and a cap wafer bonded with a frame structure, where both wafers are made of the same material to match thermal expansion, and electrically conducting vias connect device pads through the cap wafer, ensuring a sealed cavity and mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different materials are used for functional wafer and cap wafer, then functional performance is improved, but thermal stress increases causing wafer breakage
Solution Approach 1:
The patent applies homogeneity by using the same material (e.g., silicon) for both the functional wafer and cap wafer. This ensures identical thermal expansion coefficients, eliminating thermal stress during temperature changes and preventing wafer breakage, while still achieving the desired functional performance through proper device design and cavity formation.
2Stability of the object's composition
If cap wafer thickness is increased, then mechanical stability is improved, but thermal stress increases due to material differences
Solution Approach 1:
By using the same material for both wafers, the patent eliminates thermal stress regardless of cap wafer thickness. This allows the cap wafer to be optimized for mechanical stability and cavity sealing requirements without being constrained by thermal expansion mismatches that would occur with different materials.
3Reliability
If anisotropic crystal cut wafers are used, then piezoelectric device performance is improved, but thermal expansion differences along crystal axes increase wafer breakage risk
Solution Approach 1:
The patent uses identical anisotropic crystal cut wafers for both functional and cap layers, ensuring that thermal expansion behavior is matched along all crystal axes. This maintains the piezoelectric performance benefits of anisotropic materials while eliminating the thermal stress problems that would arise from material differences.
4Adaptability or versatility
If wafer bonding is performed with different materials, then device functionality is achieved, but thermal stress during bonding and processing increases scrap rates
Solution Approach 1:
By bonding identical materials together, the patent eliminates thermal stress during wafer bonding and subsequent processing steps. This dramatically reduces wafer breakage and scrap rates, improving manufacturing yield while still achieving the required device functionality through proper bonding interface design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the risk of wafer damage and scrap by minimizing thermal stress and maintaining mechanical stability, allowing for efficient manufacturing of micro-acoustic devices like resonators and filters with reduced surface area requirements.
Implementation Method 1
The cap wafer is bonded with the inner surface to the first surface of the functional wafer
Implementation Method 2
The frame structure seals to the first surface and to the inner surface as well
Implementation Method 3
Electrically conducting vias are guided through the cap wafer and connect the inner cap pads with package pads arranged on the outer surface
Data Source
AI summary
A wafer level package comprises a functional wafer with a first surface, device structures connected to device pads arranged on the first surface. A cap wafer, having an inner and an outer surface, is bonded with the inner surface to the first surface of the functional wafer. A frame structure surrounding the device structures is arranged between functional wafer and cap wafer. Connection posts are connecting the device pads on the first surface to inner cap pads on the inner surface. Electrically conducting vias are guided through the cap wafer connecting inner cap pads on the inner surface and package pads on the outer surface of the cap wafer.