Wafer Permanent Carrier Anodic Bonding
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in producing stronger wafers to prevent breakage during handling, as temporary wafer carriers increase manufacturing time and cost, and limit the maximum temperature for fabrication due to bonding and de-bonding requirements.
Innovation Solution
A semiconductor device with a permanent carrier wafer bonded over a conductive layer, utilizing anodic bonding to create a strong and durable interconnect structure that allows for higher temperature processing, enhancing wafer strength and reducing the risk of damage during handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a temporary wafer carrier is bonded to the wafer to increase strength and prevent breakage, then wafer durability is improved, but manufacturing time increases due to bonding and de-bonding requirements
Solution Approach 1:
The patent removes the temporary carrier from the manufacturing process entirely by making the wafer itself self-supporting through thickness increase. This extraction eliminates the bonding and de-bonding steps that consume manufacturing time, while the wafer's enhanced thickness provides the necessary durability without requiring an external temporary carrier.
Solution Approach 2:
The patent eliminates the need for temporary carriers (disposable objects used only during manufacturing) by making the wafer itself permanent and self-supporting. This removes the entire class of temporary support structures from the process, reducing both time and complexity.
2Strength
If a temporary wafer carrier is used to strengthen the wafer, then wafer strength is improved, but the maximum processing temperature is limited due to bonding material constraints
Solution Approach 1:
The patent extracts the temporary carrier and its bonding materials from the system, replacing them with a self-supporting wafer structure. This eliminates the temperature limitation imposed by bonding material constraints, allowing processing temperatures to exceed 200°C without risking carrier bond failure.
3Strength
If wafer thickness is increased to prevent breakage during handling, then wafer strength is improved, but wafer level integration density is reduced
Solution Approach 1:
The patent addresses the strength-density tradeoff by transitioning from two-dimensional thin wafer structures to three-dimensional thicker wafer structures with embedded conductive vias. This dimensional change allows the wafer to maintain mechanical strength through increased thickness while preserving integration density through vertical via structures that connect multiple conductive layers within the thicker substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The permanent bonding of the carrier wafer enables increased wafer durability and allows for higher temperature processing, reducing yield loss and fabrication downtime while maintaining the integrity of the semiconductor device.
Implementation Method 1
utilizing anodic bonding to create a strong and durable interconnect structure
Data Source
AI summary
A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.