Wafer Patterning via Positive Resist Inversion and Merged Lithography
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Solution Overview
Problem
Current semiconductor fabrication methods using negative photoresists for lithography are inefficient and lack suitable options for the 32 nm International Technology Roadmap for Semiconductors (ITRS) node, and methods involving sequential interleaved lithography exposures are cumbersome, leading to overlay errors and increased process steps.
Innovation Solution
The method involves transferring approximately an inverse of patterned features from a positive resist layer to a device material on a wafer using two interleaved exposures without intermediate develop or etch processes, utilizing different reticles and sacrificial layers to form precise device structures, such as transistor gate structures, with dimensions less than 40 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If negative photoresist is used for lithography, then lithography can be performed, but the process is inefficient and lacks suitable options for the 32 nm ITRS node
Solution Approach 1:
The patent inverts the conventional approach by using positive photoresist instead of negative photoresist for the first lithography exposure. This inversion allows the formation of first patterned features that are subsequently used as masks, eliminating the need for negative tone resists and enabling efficient patterning at the 32 nm node while maintaining process reliability
2Manufacturing precision
If etching is performed between interleaved photolithography patterning steps, then pattern transfer can be achieved, but the cycle time and number of process steps are doubled
Solution Approach 1:
The patent merges the pattern transfer function into the lithography process itself by using the first patterned features as direct masks for the second lithography exposure. This eliminates the need for separate etching steps between lithography exposures, reducing the cycle time and number of process steps while maintaining pattern transfer accuracy through the mask function of the first patterned features
3Manufacturing precision
If overlay error between first and second patterned resist is reduced, then final etched feature width is improved, but this requires precise alignment control
Solution Approach 1:
The patent extracts the alignment control requirement from the resist layer by using the first patterned features (which are more robust and easier to form) as masks for the second exposure. This approach reduces overlay error sensitivity and simplifies alignment control, as the mask features provide stable reference points for positioning the second pattern without requiring complex real-time alignment adjustments
4Manufacturing precision
If second resist is coated over first patterned resist, then second pattern can be formed, but significant non-uniformity occurs due to topography
Solution Approach 1:
The patent performs preliminary pattern formation and removal of the first resist before applying the second resist. This preliminary action eliminates the topography-induced non-uniformity that would occur if the second resist were coated over the first patterned resist, as the first resist is completely removed leaving a flat surface for uniform second resist coating and subsequent pattern formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overlay errors, eliminates the need for negative tone resists, and simplifies the process, enabling the formation of precise device structures with reduced cycle time and cost, while meeting the requirements of the 32 nm ITRS node.
Implementation Method 1
The resist may, therefore, be patterned by selectively exposing regions of the resist to an energy source such as ultraviolet light, a beam of electrons, or an x-ray source
Data Source
AI summary
Methods for forming device structures on a wafer are provided. One method includes transferring approximately an inverse of patterned features formed in a positive resist layer on the wafer to a device material on the wafer to form the device structures in the device material. Another method includes transferring approximately an inverse of patterned features formed in a sacrificial layer on the wafer to a device material on the wafer to form the device structures in the device material.