Semiconductor Wafer Scribe Structure for Flexible Thin-Wafer Dicing
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Solution Overview
Problem
Existing sawing processes for semiconductor wafers, particularly those with thin thicknesses, face challenges such as stress and damage to chip regions due to the application of certain dicing methods, limiting the applicability of these methods and reducing productivity.
Innovation Solution
A semiconductor wafer structure design that includes chip regions, a scribe region with trenches and dummy structures, allowing for various sawing processes like blade, laser, and plasma dicing by incorporating a first, second, and third trench configuration, enabling flexible dicing methods regardless of wafer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If certain dicing methods are applied to thin semiconductor wafers, then productivity is improved, but stress and damage to chip regions occur
Solution Approach 1:
The scribe region is divided into multiple trenches (first trench along first side, second trench along second side, third trench in between) instead of a single cut line. This segmentation allows different dicing methods to be applied to different trenches, enabling thin wafers to be processed without stress concentration that would occur with a single deep cut, thereby improving productivity while reducing damage to chip regions.
2Adaptability or versatility
If a single dicing method is used, then process simplicity is maintained, but applicability to different wafer thicknesses is limited
Solution Approach 1:
The scribe region structure is designed with multiple trenches that can serve different functions depending on wafer thickness. The first and second trenches along the sides can be used for blade dicing in thicker wafers, while the third trench in between can be used for laser or plasma dicing in thinner wafers. This multi-functional design allows a single wafer structure to accommodate various dicing methods and thicknesses without requiring separate designs, enhancing adaptability while maintaining manageable complexity.
Data Source
AI summary
A wafer structure includes a semiconductor substrate including chip regions and a scribe region for separating each of chip regions, an interlayer insulating layer on the first surface of the semiconductor substrate, an upper insulating layer on the interlayer insulating layer, connection structures formed within the chip regions and partially surrounded by the interlayer insulating layer and the upper insulating layer respectively. First to third trenches formed within the scribe region, and extending along a first side of the scribe region and penetrating the upper insulating layer and the interlayer insulating layer, and dummy structures disposed between the first trench and the third trench and between the second trench and the third trench and partially surrounded by the interlayer insulating layer and the upper insulating layer respectively.