Wafer Section Mounting for Fan Out WLCSP Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing fan out wafer level chip scale packages (FO-WLCSPs) are time-consuming and prone to errors, especially for large diameter wafers with many die, due to the difficulty in aligning smaller semiconductor die on carriers and the limited surface area for adhesion, leading to potential device failures during encapsulation.
Innovation Solution
The method involves singulating a semiconductor wafer into sections with multiple die each, mounting these sections in a grid pattern over a temporary carrier to reserve an interconnect area, depositing an encapsulant, forming a build-up interconnect structure, and then singulating to separate the die with a portion of the interconnect area, enhancing interconnect capability and reducing alignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual semiconductor die are singulated and mounted to a temporary carrier, then each die can be packaged individually, but the process becomes time-consuming and error-prone due to alignment difficulties
Solution Approach 1:
Multiple individual die mounting operations are merged into a single wafer-level mounting operation. The entire wafer containing multiple die is mounted to the temporary carrier as one unit, eliminating the need for repeated pick-and-place operations for each individual die, thereby reducing manufacturing time while maintaining reliability through consistent wafer-level alignment
2Length of moving object
If smaller semiconductor die are used to achieve smaller device footprint, then power consumption decreases and performance improves, but alignment becomes increasingly difficult and adhesion surface area decreases
Solution Approach 1:
The alignment problem is shifted from the die level to the wafer level. By performing alignment and mounting operations on the entire wafer rather than individual small die, the effective alignment target size increases dramatically, making alignment much easier and more precise despite the small size of individual die. This dimensional shift from micro (die) to macro (wafer) level resolves the alignment precision issue
3Area of moving object
If smaller semiconductor die are mounted to the carrier, then device size decreases, but the surface area for adhesion decreases leading to shifting during encapsulation
Solution Approach 1:
The adhesion problem is resolved by shifting the bonding interface from the small die surface to the large wafer back surface. The wafer-level mounting provides a much larger adhesion surface area, ensuring strong bonding and preventing shifting during encapsulation, while the final device still achieves small footprint through the small die size
4Ease of manufacture
If wafer singulation is performed before mounting, then individual die can be handled separately, but the process becomes more complex and error-prone
Solution Approach 1:
The conventional sequence of operations is inverted: instead of singulating die first and then mounting them individually, the wafer is mounted to the temporary carrier first while still intact, and then singulated after mounting. This inversion simplifies the manufacturing process by eliminating complex individual die handling and alignment operations, reducing process complexity and errors
Data Source
AI summary
A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections.