3D Wafer Stacking with Oxide Bonding and Carrier Removal

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Solution Overview

Problem

Conventional wafer bonding methods for 3D IC technology face limitations such as process temperature constraints, potential damage to thin wafers, and compatibility issues with carrier materials, leading to alignment failures and inefficiencies in carrier removal.

Innovation Solution

A novel wafer stacking process utilizing oxide-to-oxide bonding and direct grinding or etching of sacrificial carriers, eliminating the need for adhesive-based removal methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If thermal sliding method is used to remove carrier, then carrier removal is achieved, but process temperature limitation restricts the method's applicability

Engineering Contradiction:
Improvecarrier removal easeVSAvoidprocess temperature limitation
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent replaces thermal sliding method with mechanical peeling method for carrier removal. Instead of using heat to slide the carrier off, the invention uses mechanical force to peel the carrier away from the wafer, thereby avoiding temperature limitations and expanding process compatibility.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The invention changes the removal mechanism from thermal-based to mechanical-based, fundamentally altering the process parameter from temperature-controlled to force-controlled. This parameter change enables carrier removal in temperature-sensitive processes while maintaining effectiveness.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If mechanical peeling method is used to remove carrier, then carrier removal is achieved, but wafer damage may occur during the process

Engineering Contradiction:
Improvecarrier removal easeVSAvoidwafer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-coating the carrier with a release agent before wafer bonding. This preliminary step creates a controlled interface that allows for clean carrier removal after bonding, preventing wafer damage during the peeling process while maintaining ease of carrier removal.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If laser debonding method is used to remove carrier, then carrier removal is achieved, but equipment complexity and cost increase

Engineering Contradiction:
Improvecarrier removal easeVSAvoidlaser equipment complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent employs a disposable carrier design with integrated release features that enable simple mechanical removal. This approach replaces expensive, complex laser debonding equipment with basic mechanical tools, significantly reducing equipment complexity and cost while maintaining effective carrier removal capability.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

4Strength

If adhesive method is used to bond carrier to wafer, then strong bonding is achieved, but removal process becomes complex and limited

Engineering Contradiction:
Improvebonding strengthVSAvoidremoval process complexity
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by coating the carrier with a release agent before bonding the wafer. This creates a layered structure where the wafer bonds strongly to the carrier through the release agent layer, enabling strong bonding during processing while allowing for simple mechanical removal afterward by peeling at the release agent interface.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient integration of multiple wafers in 3D IC architecture without the drawbacks of conventional carrier removal techniques, enhancing device density and performance.

Implementation Method 1

bonding said silicon oxide layer on the front side of the sacrificial carrier with the dielectric layer on the front side of the silicon substrate

Methodology Applied
Scientific EffectOxide-to-oxide bonding: Chemical Bonding

Implementation Method 2

performing a thinning process on a back side of the silicon substrate to remove parts of the silicon substrate and expose the TSVs inside

Methodology Applied
Scientific EffectPhysical removal: Abrasion

Implementation Method 3

carrier is grinded out or etched directly through physical method

Methodology Applied
Scientific EffectGrinding: Abrasion

Implementation Method 4

carrier is grinded out or etched directly through physical method

Methodology Applied
Scientific EffectEtching: Chemical Bonding

Data Source

PatentUS12610797B2Wafer stacking process
Publication Date: 2026.04.21 POWERCHIP SEMICON MFG CORP
  • US12610797B2 patent drawing
  • US12610797B2 patent drawing
  • US12610797B2 patent drawing

AI summary

A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.