Wafer Stacking via Dielectric Bonding for High Density Interconnects
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Solution Overview
Problem
Current methods for manufacturing stacked integrated circuits face challenges in achieving high performance, density, and reduced costs, particularly in bonding wafers with different fabrication processes while ensuring reliable interconnect structures and preventing diffusion spikes that can cause shorts.
Innovation Solution
A method involving the formation of interconnect structures through wafers with inter-layer dielectric layers, using metallic materials and barrier layers, and dielectric-to-dielectric bonding processes to stack wafers with precise trench and opening formations, along with planarizing and passivation layers to ensure reliable electrical connections and prevent shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafers with different fabrication processes are stacked to increase density and reduce footprint, then integration density and performance are improved, but the risk of diffusion spikes causing shorts between layers increases
Solution Approach 1:
A bonding dielectric layer is introduced as an intermediary between the first and second wafers during stacking. This bonding dielectric prevents diffusion spikes from forming at the interface between wafers with different fabrication processes, thereby eliminating the short circuit risk while maintaining high integration density through 3D stacking.
Solution Approach 2:
Interconnect structures are formed penetrating through the first substrate and into the first inter-layer dielectric layer before the stacking process. This preliminary formation of interconnect structures ensures proper electrical connections are established prior to bonding, preventing diffusion-related shorts while enabling high-density integration.
2Reliability
If interconnect structures are formed by penetrating through substrates and depositing metallic materials, then reliable electrical connections are achieved, but the process complexity and manufacturing difficulty increase
Solution Approach 1:
The interconnect structure formation is segmented into distinct steps: forming openings/trenches, depositing barrier layers, depositing metallic materials, and planarizing. This segmentation allows each step to be optimized independently, achieving reliable electrical connections while managing manufacturing complexity through standardized process modules.
Solution Approach 2:
The same interconnect formation process (opening formation, barrier layer deposition, metallic material deposition, planarization) is applied universally to both the first and second wafers. This multi-functional approach ensures consistent electrical connection reliability across different layers while using standardized manufacturing steps to control process complexity.
3Manufacturing precision
If multiple planarizing processes are performed to remove excess materials, then manufacturing precision and interconnect reliability are improved, but production time and process duration increase
Solution Approach 1:
Planarizing processes are performed preliminarily after each interconnect structure formation step to remove excess materials and create flat surfaces. This preliminary planarization ensures precise alignment and reliable connections for subsequent stacking and interconnect formation steps, while the systematic timing of these operations optimizes overall production time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient stacking of wafers with different fabrication processes, enhancing performance and density while preventing diffusion spikes and ensuring reliable electrical connections, thus addressing the challenges of existing technologies.
Implementation Method 1
bonding a second wafer on the first wafer, wherein the second wafer comprises a second substrate, a second ILD layer disposed on a second front surface of the second substrate
Implementation Method 2
depositing a first metallic material in the first opening
Implementation Method 3
depositing a second metallic layer in the first trench, the second trench and recess
Implementation Method 4
depositing a first barrier layer on the first insulator and the one of the first conductors before the deposition of the first metallic material
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.