Wafer Test Circuit Interconnection via Scribe Line Routing
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Solution Overview
Problem
Current semiconductor wafer testing techniques are inefficient due to the time-consuming process of placing probe card needles on multiple sites, as the test circuits in scribe lines are destroyed during chip division, limiting simultaneous testing across the wafer.
Innovation Solution
The implementation of vertical and horizontal routing lines in scribe lines to interconnect test sites, allowing simultaneous connection of probe card needles to multiple test circuit sites with integrated circuit select and control circuitry, voltage regulators, and sensor circuit banks, enabling access to all test sites from a single location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If probe card needles are placed on multiple sites to test all test circuits, then testing completeness is improved, but testing time increases significantly
Solution Approach 1:
The wafer is divided into multiple test sites arranged in rows and columns, with each site containing test circuits in the scribe lines. This segmentation allows systematic organization of test circuits while enabling efficient access patterns that reduce overall testing time compared to traditional multi-site probing.
Solution Approach 2:
A single probe card needle configuration can access and test all test circuits across multiple sites through the organized row-column structure. The universal access method eliminates the need for repositioning or multiple specialized probe setups, thereby reducing testing time while maintaining complete test coverage.
2Productivity
If test circuits are placed in scribe lines for wafer level testing, then testing efficiency is improved, but the test circuits are destroyed during chip division
Solution Approach 1:
All test circuits are tested on the wafer before the scribe line cutting process. The organized test site structure enables comprehensive testing to be completed in advance, ensuring test circuit integrity is maintained by performing all necessary measurements before the destructive cutting operation occurs.
3Reliability
If multiple probe card needles are used to access different test sites, then testing coverage is improved, but operation complexity increases
Solution Approach 1:
Test sites are segmented into organized rows and columns with standardized configurations. This systematic segmentation simplifies the operation by providing a predictable pattern for probe card needle placement and movement, reducing operational complexity while maintaining comprehensive test coverage.
Solution Approach 2:
The test site configuration uses standardized parameters for pad arrangements and circuit layouts across all sites. This parameter standardization enables simpler probe card designs and easier operational procedures while ensuring complete testing coverage through consistent site structures.
Data Source
AI summary
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.