Semiconductor Wafer Test Module Pin Matrix Addressing
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Solution Overview
Problem
Existing test modules for semiconductor wafers face challenges in efficiently utilizing wafer scribe line area, requiring extensive component count and test time due to the need for multiplex circuitry and limited pin availability, which restricts the number of devices that can be tested simultaneously.
Innovation Solution
Implementing pin matrixed addressing with locally shared pins for device terminals, allowing for independent access and selection of devices without additional circuitry, enabling parallel testing of multiple MOS devices using Source-Measure Units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiplex circuitry is used to increase the number of devices per test pin, then the number of placed devices increases, but the device complexity and test time increase due to additional circuitry requirements
Solution Approach 1:
The test module is segmented into a matrix arrangement of devices with row and column select lines, allowing independent addressing of individual devices without requiring complex multiplex circuitry. Each device can be selected by the combination of row and column signals, dividing the selection function into simpler segmental operations.
Solution Approach 2:
The test pins are given multiple functions: they serve both as device terminals and as select lines for addressing. The same pin structure is used for both signal transmission and device selection, eliminating the need for dedicated multiplex circuitry and reducing overall device complexity.
2Quantity of substance
If a standard 1×16 TM is used with global pin sharing, then the number of MOS devices increases to 12, but the wafer area efficiency decreases and test time increases
Solution Approach 1:
The test module transitions from a one-dimensional linear arrangement to a two-dimensional matrix arrangement. Devices are organized in rows and columns, allowing the same number of pins to address a larger number of devices by utilizing the additional spatial dimension, thereby increasing device density without proportionally increasing pin count or area.
Solution Approach 2:
Multiple device terminals are merged onto shared pin structures. The row select lines and column select lines are combined with device terminal connections, allowing the same physical pins to serve dual purposes of both selecting devices and providing electrical connections, thus reducing the total pin count required for a given number of devices.
3Quantity of substance
If multiplex circuitry is implemented for device selection, then more devices can be tested, but the test time increases due to sequential access requirements
Solution Approach 1:
The device selection is performed in advance through the matrix addressing scheme, where row and column select lines are prepared and applied simultaneously to identify the target device before actual testing begins. This preliminary addressing action enables direct access to the selected device without sequential scanning, reducing test time.
Solution Approach 2:
The matrix addressing system allows continuous parallel operation of multiple test functions. While one device is being tested, other devices can be pre-selected or configured, maintaining continuous useful action throughout the test process rather than having idle periods between device selections.
Data Source
AI summary
A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.