Wafer Test Pad with Distributed Vias for Low-Force Probing
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Solution Overview
Problem
The introduction of three-dimensional integrated circuits (3DIC) leads to depth loading issues in probing wafer acceptance test (WAT) pads due to the planarization of passivation layers, requiring excessive probing force that can damage probe cards.
Innovation Solution
Implementing a WAT pad electrically coupled to a top metal layer via a plurality of smaller contact vias distributed over the pad, eliminating depth loading effects and ensuring minimal probing force is required for access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large via is used to access the WAT pad, then electrical contact is achieved, but depth loading occurs requiring excessive probing force that can damage probe cards
Solution Approach 1:
The patent divides the single large via into multiple smaller contact vias distributed across the WAT pad. This segmentation reduces the depth loading effect at each individual via while maintaining the total electrical contact area, thereby reducing the probing force required and preventing damage to probe cards.
Solution Approach 2:
The patent applies different via sizes at different locations on the WAT pad. Larger vias are positioned where less probing force is needed, while smaller vias are distributed to reduce depth loading. This local differentiation optimizes both electrical contact and probing force requirements.
2Adaptability or versatility
If the passivation layer is planarized to provide a planar top surface for chip stacking, then vertical stacking is enabled, but depth loading issues arise in probing WAT pads
Solution Approach 1:
By segmenting the via structure into multiple smaller vias, the patent maintains planarization benefits for chip stacking while eliminating the depth loading problem that would otherwise compromise probing accessibility.
Solution Approach 2:
The patent transitions from a single-point via approach to a distributed multi-point via approach, utilizing the spatial dimension across the WAT pad surface to reduce depth loading while maintaining electrical contact.
3Force
If multiple smaller contact vias are used instead of a single large via, then depth loading is eliminated and probing force is reduced, but via count and structural complexity increase
Solution Approach 1:
While segmentation increases the number of vias, it is implemented in a controlled manner where only the necessary number of vias are created to achieve the desired electrical contact and reduce depth loading. The segmentation is optimized to balance complexity reduction with functional requirements.
Data Source
AI summary
A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.