Wafer Thickness Reduction via Anisotropic Etching
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Solution Overview
Problem
Current methods for reducing the size of electronic components and MEMS devices face challenges such as limited aspect ratios in wet etching, high costs and slow throughput in dry etching, and risks of wafer damage in mechanical thinning, which hinder efficient manufacturing and increase costs.
Innovation Solution
A method involving anisotropic etching from the back surface of a wafer to form recesses and reduce thickness, using a masking material applied via photolithography, which allows for precise reduction of wafer thickness without mechanical processing, enabling deeper recesses and increased capacity in MEMS device manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wet etching is used to form cavities from the back surface, then the etching process is simple and fast, but only relatively small aspect ratios can be achieved requiring wider cavities which waste wafer estate
Solution Approach 1:
The patent replaces wet etching (chemical process) with dry etching (physical/chemical process) to achieve high aspect ratio cavities. The dry etching process uses plasma to physically sputter and chemically react with the silicon material, enabling vertical cavity walls and high aspect ratios while maintaining etching speed through optimized process parameters.
Solution Approach 2:
The patent changes the etching parameters by using a two-stage dry etching process with different gas compositions and power settings. The first stage uses CF4/O2 plasma for anisotropic etching to create vertical walls, while the second stage adjusts parameters to complete the cavity formation, achieving high aspect ratios without increasing cavity width.
2Manufacturing precision
If dry etching is used to achieve high aspect ratios, then the cavity depth-to-width ratio is improved, but the process is relatively slow and expensive requiring multiple equipment batches
Solution Approach 1:
The patent segments the etching process into multiple stages with different parameters. The first dry etching stage creates the initial cavity structure with high aspect ratio, while subsequent stages complete the formation. This segmentation allows each stage to be optimized for its specific function, achieving high precision while maintaining reasonable throughput through parallel processing capabilities.
Solution Approach 2:
The patent makes a single dry etching equipment perform multiple functions by implementing a two-mode operation: first as an anisotropic etcher for vertical cavity walls, then as a completion etcher for final cavity formation. This multi-functionality eliminates the need for separate equipment batches and reduces manufacturing costs while maintaining high aspect ratio precision.
3Length of stationary object
If mechanical wafer thinning techniques such as grinding are used, then the wafer thickness can be reduced, but the risk of damaging the wafer and MEMS structures increases below a certain minimal thickness
Solution Approach 1:
The patent replaces mechanical wafer thinning (grinding) with chemical etching processes. The wafer thickness is reduced through controlled chemical removal of material via wet and dry etching, which eliminates mechanical contact and associated damage risks. This allows thickness reduction below the minimal threshold safe for mechanical processes while maintaining wafer integrity through precise chemical control and protective masking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of thinner wafers with deeper recesses, reducing manufacturing costs and increasing capacity, while minimizing the risk of wafer damage, and allows for more efficient processing of large-diameter wafers with improved signal-to-noise ratio and processing efficiency in MEMS devices like silicon microphones.
Implementation Method 1
applying a masking material at the second main surface and structuring the masking material to obtain a plurality of masked areas and a plurality of unmasked areas
Implementation Method 2
anisotropically etching the wafer from the second main surface at the unmasked areas to form a plurality of recesses
Implementation Method 3
removing the masking material at least at some of the masked areas to obtain previously masked areas
Implementation Method 4
anisotropically etching the wafer from the second main surface at the unmasked areas and the previously masked areas to increase a depth of the recesses and reduce a thickness of the wafer
Data Source
AI summary
A method for processing a wafer having microelectromechanical system structures at the first main surface includes applying a masking material at the second main surface and structuring the masking material to obtain a plurality of masked areas and a plurality of unmasked areas at the second main surface. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas to form a plurality of recesses. The masking material is then removed at least at some of the masked areas to obtain previously masked areas. The method further includes anisotropically etching the wafer from the second main surface at the unmasked areas and the previously masked areas to increase a depth of the recesses and reduce a thickness of the wafer at the previously masked areas.