Semiconductor Wafer Thinning with Two-Step Grinding and CMP

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Solution Overview

Problem

The thinning process of semiconductor device substrates results in significant thickness variations and defects, particularly in thinner regions, which affects the performance and reliability of 3D integrated circuits.

Innovation Solution

A method involving adhesive coating, two-step grinding, and chemical mechanical polishing (CMP) processes is employed to achieve uniform thickness and reduce defects, with parameters adjusted based on real-time thickness variations and profiles to achieve sub-micron thicknesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a substrate is thinned during fabrication to reduce total height and interconnect lengths, then power consumption and parasitic resistance are reduced, but significant variations in thickness and formation of defects occur

Engineering Contradiction:
Improvepower consumptionVSAvoidthickness uniformity
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The thinning process is divided into multiple sequential steps (first grinding process, second grinding process, and CMP process) with each step targeting specific thickness ranges and removing different types of defects. The first grinding process removes thick material down to intermediate thickness, the second grinding process further thins to near-final thickness, and the CMP process achieves final uniform thickness, with each step contributing to overall thickness uniformity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Grinding processes are performed before the CMP process to pre-thin the substrate and remove major defects. This preliminary mechanical removal of material reduces the burden on the subsequent CMP process, allowing it to focus on achieving final thickness uniformity and surface quality rather than removing large amounts of material

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a substrate is thinned to reduce interconnect lengths, then parasitic resistance and capacitance are reduced, but defects form in thinner regions

Engineering Contradiction:
Improvedevice reliabilityVSAvoiddefects in thinner regions
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The thinning process is segmented into multiple steps with each step addressing specific defect types. The first grinding process removes surface defects and contaminants, the second grinding process addresses subsurface defects and prepares for final thinning, and the CMP process removes grinding-induced defects while achieving final thickness uniformity and surface quality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The grinding processes, which initially might be expected to create defects, are used strategically to remove defective material and prepare the substrate for defect-free final thinning. The controlled mechanical removal converts potential harm (grinding-induced stress) into benefit (defect removal and surface preparation) when followed by the defect-removing CMP process

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves uniform substrate thinning to sub-micron levels, reducing defects such as cracks and delamination, and improves the reliability and performance of semiconductor devices by minimizing thickness variations.

Implementation Method 1

a carrier wafer is bonded to a frontside surface of the device wafer using an adhesive material

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

performing a first grinding process to thin the device wafer from a first thickness to a second thickness

Methodology Applied
Scientific EffectAbrasion: Abrasion

Implementation Method 3

performing a chemical mechanical polish (CMP) process to thin the device wafer from the third thickness to a fourth thickness

Methodology Applied
Scientific EffectChemical mechanical polishing:

Data Source

PatentUS20250205845A1Methods for thinning substrates for semiconductor devices
Publication Date: 2025.06.26 QORVO US INC
  • US20250205845A1 patent drawing
  • US20250205845A1 patent drawing
  • US20250205845A1 patent drawing

AI summary

Methods and systems for thinning a device wafer to tens of micron, micron, or sub-micron thicknesses are disclosed. Device wafers are thinned by using a two-step grinding process and a chemical mechanical polish (CMP) process. One or more first grinding parameters associated with the first grinding process are determined, received, and/or adjusted before and/or during the performance of the first grinding process. One or more second grinding parameters associated with the second grinding process are determined, received and/or adjusted before and/or during the performance of the second grinding process. One or more polishing parameters associated with the CMP process are determined and/or adjusted before and/or during the performance of the CMP process.