Semiconductor Wafer Pre-Sawing Via Defect Detection
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Solution Overview
Problem
In stacked-chip packaging, defects such as incomplete via holes and uneven conductive metal plating can result in open circuits between through silicon vias (TSVs) and the bottommost patterned metal layer, which are only detected after the semiconductor wafer has been sawed into dice, leading to yield loss and delayed defect identification.
Innovation Solution
A semiconductor package and process that includes a semiconductor die with a substrate, dielectric layers, and integrated circuits, where a metal segment is exposed laterally and insulated from the integrated circuit, allowing for the formation of testing holes and conductive metals that contact the bottommost patterned metal layer, enabling pre-sawing defect detection by probing the conductive metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor wafer is sawed into dice before testing, then the manufacturing process can proceed to packaging, but defects in conductive vias cannot be detected until after packaging, leading to yield loss
Solution Approach 1:
The patent performs via connection testing before the wafer is sawed into individual dice. Testing holes are formed through the substrate to expose both the metal segment and the bottommost patterned metal layer, allowing conductive metal to be plated and tested for proper via formation. This preliminary testing identifies defective vias before they are incorporated into packaged devices, preventing yield loss while maintaining manufacturing throughput.
2Measurement precision
If testing holes are formed to expose the bottommost patterned metal layer for via testing, then via defects can be detected early, but the testing process becomes more complex
Solution Approach 1:
The patent segments the testing function by creating separate testing holes that are distinct from the actual via holes. The testing holes expose both the metal segment and the bottommost patterned metal layer independently, allowing for dedicated via formation and testing structures. This segmentation enables precise defect detection while keeping the testing process separate from the main via fabrication, thereby managing complexity.
3Loss of time
If the metal segment is exposed from the lateral side surface for testing, then pre-sawing defect detection is enabled, but additional processing steps are required
Solution Approach 1:
The patent merges the exposure of the metal segment with the existing lateral side surface of the semiconductor die. By forming testing holes that extend through the substrate to expose the metal segment at the lateral surface, the design combines the testing functionality with the existing die structure. This integration enables early defect detection without requiring completely separate processing steps, balancing manufacturing simplicity with timely defect identification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the identification of defects in conductive vias before sawing the wafer, enhancing yield by ensuring that only qualified vias are used in the final semiconductor dice, thereby reducing waste and improving manufacturing efficiency.
Implementation Method 1
the via holes are plated with a conductive metal so as to form the through silicon vias (TSVs)
Data Source
AI summary
The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.