Wakeup-Free Ferroelectric Memory Device Using Electronegativity

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Solution Overview

Problem

Ferroelectric memory cells require a wakeup procedure to restore the memory window after power disconnection, which increases power consumption and occupies valuable space on integrated circuits, limiting the density and performance of ferroelectric random-access memory (FeRAM) devices.

Innovation Solution

A wakeup-free ferroelectric memory device is designed with a polarization switching structure where the ferroelectric structure is sandwiched between conductive structures with overall electronegativity greater than or equal to the ferroelectric structure, eliminating the need for a wakeup procedure by maintaining the memory window without power degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a wakeup procedure is implemented to restore the memory window after power disconnection, then the ferroelectric memory device can maintain data integrity, but power consumption increases and device density decreases

Engineering Contradiction:
Improvememory window restorationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by forming conductive structures with specific electronegativity characteristics before power disconnection occurs. These pre-configured conductive structures (with electronegativity greater than or equal to the ferroelectric structure) automatically maintain the memory window without requiring post-power-off wakeup procedures, thus preventing the need for additional power-consuming restoration operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a wakeup procedure is implemented to restore the memory window after power disconnection, then the ferroelectric memory device can maintain data integrity, but valuable space on integrated circuits is occupied

Engineering Contradiction:
Improvememory window restorationVSAvoidintegrated circuit space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses preliminary action by configuring the conductive structures with appropriate electronegativity during the initial device fabrication process. This pre-configuration eliminates the need for separate wakeup circuitry that would otherwise be required to restore the memory window, thereby freeing up valuable integrated circuit space while maintaining data integrity.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If conventional ferroelectric memory structures are used, then the device can store data, but the memory window degrades after power disconnection requiring additional restoration steps

Engineering Contradiction:
Improvedata storage capabilityVSAvoidmemory window stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The patent applies parameter changes by modifying the electronegativity parameter of the conductive structures. By selecting conductive materials or structures with electronegativity greater than or equal to the ferroelectric structure, the patent fundamentally changes the electrical characteristics of the memory device, enabling the memory window to remain stable after power disconnection without degrading.

Inventive Principle:
Principle #35Parameter changes

4Productivity

If the density of ferroelectric memory devices is increased on integrated circuits, then more data can be stored, but the wakeup circuitry occupies valuable space

Engineering Contradiction:
Improvememory device densityVSAvoidintegrated circuit space
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the wakeup procedure from the ferroelectric memory device architecture. By removing this unnecessary component through the use of conductive structures with appropriate electronegativity, the patent frees up space that would have been required for wakeup circuitry, thereby enabling higher memory device density on integrated circuits.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces power consumption and allows for a higher density of ferroelectric memory devices on integrated circuits, as the memory window is maintained without the need for a wakeup procedure, enhancing the performance and efficiency of FeRAM devices.

Implementation Method 1

a polarization switching structure comprising a ferroelectric structure disposed between a first conductive structure and a second conductive structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure

Methodology Applied
Scientific EffectFerroelectric polarization:

Implementation Method 2

both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure

Methodology Applied
Scientific EffectElectronegativity effect:

Data Source

PatentUS20230197847A1Wakeup-free ferroelectric memory device
Publication Date: 2023.06.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230197847A1 patent drawing
  • US20230197847A1 patent drawing
  • US20230197847A1 patent drawing

AI summary

The present disclosure relates to a method for forming a ferroelectric memory device. The method includes forming a dielectric layer over a semiconductor substrate and forming a first conductive layer over the dielectric layer. The first conductive layer has a first overall electronegativity. A ferroelectric layer is formed on the first conductive layer. The ferroelectric layer has a second overall electronegativity less than or equal to the first overall electronegativity. A second conductive layer is formed on the ferroelectric layer. The second conductive layer has a third overall electronegativity greater than or equal to the second overall electronegativity. The second conductive layer, the ferroelectric layer, and the first conductive layer are etched to form a polarization switching structure. An ILD layer is formed over the polarization switching structure, and a planarization process is performed on the ILD layer. A first conductive via is formed over the polarization switching structure.