Wall Fin Structure for GAA FET Gate Control at Scaled Nodes
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving full gate control over the channel region, particularly the bottom part, in devices like Fin FETs and GAA FETs, leading to issues such as short-channel effects and reduced performance as transistor dimensions shrink to sub-10-15 nm nodes.
Innovation Solution
The implementation of a wall fin structure with a stacked layer of semiconductor layers and a high-k dielectric material to isolate and define the source/drain epitaxial layers, combined with a sacrificial cladding layer and multiple dielectric layers to enhance gate control and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to sub-10-15 nm nodes, then device density and integration are improved, but gate control over the channel region deteriorates
Solution Approach 1:
The patent transitions from planar 2D gate control to three-dimensional gate-all-around structures that wrap around the channel region in multiple dimensions. This includes FinFET configurations where the gate surrounds three sides of a vertical fin, and GAA FET configurations where the gate completely encircles the channel, providing control from top, bottom, and all sidewalls. This dimensional evolution enables effective gate control at sub-10-15 nm nodes by utilizing vertical stacking and multi-directional wrapping rather than relying solely on lateral scaling.
Solution Approach 2:
The gate structure is nested around the channel region in a concentric arrangement, with the gate electrode completely surrounding the channel in GAA FET configurations. This nested geometry allows the gate to control the channel from all directions simultaneously, maximizing electrostatic control and enabling continued scaling to sub-10-15 nm nodes while maintaining effective carrier modulation.
2Device complexity
If gate structure surrounds the fin on three surfaces (Fin FET), then manufacturing complexity is reduced compared to full surrounding, but gate control over the bottom part of the channel deteriorates
Solution Approach 1:
The patent evolves from the three-side wrapping FinFET configuration to the complete surrounding GAA FET configuration. This transition adds the bottom gate coverage dimension, transforming the gate structure from controlling only three sidewalls to controlling all four sides plus the bottom of the channel region. This additional dimensional control eliminates the uncovered bottom region present in FinFETs, achieving uniform gate control throughout the entire channel volume.
Solution Approach 2:
The patent employs composite material structures in the gate-all-around configuration, combining different dielectric materials (such as high-k dielectrics) with conductive gate materials to achieve both complete geometric surrounding and optimized electrical control. This composite approach enables the gate structure to effectively control the channel from all directions while managing the complexity through material property optimization rather than purely geometric complexity.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.