Warpage Adjusting Component in Semiconductor Package
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Solution Overview
Problem
The mismatch in Coefficients of Thermal Expansion (CTEs) between materials in semiconductor device packages leads to significant warpage, causing irregular joints and bump cracks, which adversely affects the packaging process yield.
Innovation Solution
Incorporating warpage adjusting components with a higher Young's modulus and lower CTE than the encapsulating material, disposed on second semiconductor devices, to reduce thermal expansion mismatch and improve the warpage profile, potentially using dummy dies or materials like silicon or glass.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dies are stacked vertically and horizontally onto redistribution structures using flip chip bonding, then the packaging density and integration are improved, but significant warpage occurs due to CTE mismatch between materials
Solution Approach 1:
The patent changes the physical state of the molding compound by controlling the reflow process parameters (temperature, time, atmosphere) to achieve optimal curing characteristics. This parameter optimization reduces excessive warpage while maintaining packaging density, resolving the contradiction between high integration and shape stability.
2Reliability
If molding compound is applied to cover device dies and solder balls, then the package is protected and encapsulated, but warpage is worsened due to asymmetrical arrangement of device dies
Solution Approach 1:
The patent applies preliminary underfill material to the asymmetrical regions before applying the molding compound. This preliminary action compensates for the asymmetrical stress distribution, preventing excessive warpage while maintaining the protective encapsulation function of the molding compound.
3Strength
If reflow is performed to melt solder balls for bonding, then the device dies are securely bonded to redistribution structure, but thermal expansion mismatch causes irregular joints and bump cracks
Solution Approach 1:
The patent optimizes reflow process parameters including peak temperature, dwell time, and cooling rate to control the thermal expansion and contraction cycles. This parameter control ensures strong bonding while minimizing thermal stress that causes joint irregularity and bump cracks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage and improves the packaging process yield by minimizing thermal expansion mismatch, allowing for a more stable and compact semiconductor device package without the need for additional space on the redistribution structure.
Implementation Method 1
there is significant mismatch between the Coefficients of Thermal Expansion (CTEs) of the materials in the packages
Implementation Method 2
a reflow is performed to melt the solder balls that interconnect the dies and the redistribution structure
Data Source
AI summary
A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.