Wave-Like Polysilicon Gate Layout for High Channel Density Power Devices
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Solution Overview
Problem
Conventional lateral MOSFET devices face challenges in reducing on-resistance while maintaining a compact size, as increasing channel width to enhance power management efficiency often results in increased transistor array area, and existing solutions do not effectively address the need for higher channel density for large current switching operations.
Innovation Solution
A novel layout for lateral semiconductor power devices featuring polysilicon gate regions configured in a wave-like pattern between source and drain regions, which increases channel density and width per unit area without expanding the transistor array, achieved by patterning the gate electrode layer into wave-shaped stripes to enhance current conduction area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel width is increased to reduce on-resistance, then the power management efficiency is improved, but the transistor array area increases
Solution Approach 1:
The gate electrode layer is segmented into multiple interleaved finger gates (first finger gates and second finger gates) that are arranged in an alternating pattern. This segmentation allows the channel width to be effectively increased by adding more parallel conduction paths without proportionally increasing the overall device area, as the gates share common source and drain regions.
Solution Approach 2:
The gate electrodes are extended in the lateral dimension by creating multiple interleaved fingers that span across the device. This dimensional extension of the gate structure increases the effective channel width and conduction area without requiring a proportional increase in the vertical or overall footprint of the transistor array.
2Loss of energy
If the contact and metal stripe width is increased to reduce on-resistance, then the on-resistance is reduced, but the transistor array area increases
Solution Approach 1:
Adjacent first and second finger gates are merged at their ends to share common source and drain regions. This merging strategy allows multiple gate structures to share common contact areas, reducing the total area required for contacts and metal interconnects while maintaining low on-resistance through the increased effective channel width provided by the interleaved gate configuration.
3Productivity
If the channel width per unit area is increased for large current switching, then the power management efficiency is improved, but the device complexity increases
Solution Approach 1:
The complex interleaved gate structure is extracted and implemented as a separate gate electrode layer that can be independently patterned and controlled. This extraction allows the complex multi-finger gate configuration to be realized without proportionally increasing the complexity of other device components, as the source and drain regions serve multiple gates simultaneously.
Data Source
AI summary
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.