Wide Bandgap Device Integrated Circuit Architecture on Engineered Substrate
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Solution Overview
Problem
Wide band gap semiconductor devices, such as gallium nitride (GaN) materials, face manufacturing challenges due to lattice mismatch and different coefficients of thermal expansion (CTEs) between the GaN layers and carrier substrates, leading to defects, strains, and increased costs.
Innovation Solution
Fabricating high-density, low-cost WBG integrated circuits using a large engineered substrate with a CTE matching that of the WBG epitaxial layer, allowing for thicker epitaxial layers and reduced dislocation density, thereby improving device performance and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If GaN layers are grown on a carrier substrate with different lattice structure, then GaN epitaxial layers can be formed, but defects, dislocations, and strains are created that negatively impact device yields and performance
Solution Approach 1:
The patent uses a buffer layer as an intermediary between the carrier substrate and the GaN epitaxial layers. This buffer layer has a lattice structure that gradually transitions from the substrate to the GaN layer, reducing the abrupt lattice mismatch and minimizing the generation of defects, dislocations, and strains.
Solution Approach 2:
The patent modifies the lattice structure parameter by introducing a buffer layer with intermediate lattice constant. This gradual change in lattice parameter reduces the mismatch stress and prevents the formation of misfit dislocations at the interface between the substrate and GaN layers.
2Manufacturing precision
If thermal processing is performed for GaN epitaxial growth, then GaN layers can be formed, but cracking, delamination, or substrate failure occurs due to different coefficients of thermal expansion
Solution Approach 1:
The buffer layer serves as a thermal expansion mediator between the carrier substrate and the GaN layers. Its intermediate CTE value allows it to absorb and distribute the thermal stress generated during epitaxial growth, preventing stress concentration that would lead to cracking or delamination.
Solution Approach 2:
The patent changes the thermal expansion parameter by introducing a buffer layer with CTE that is intermediate between the substrate and GaN. This gradual transition in thermal expansion properties reduces the thermal mismatch stress during high-temperature processing, preventing substrate failure.
3Productivity
If different coefficients of thermal expansion are present between substrate and GaN, then epitaxial growth can proceed, but substrate wafer size is restricted, limiting scale and preventing cost reduction
Solution Approach 1:
The buffer layer acts as a thermal expansion mediator that enables the use of larger substrate wafers. By distributing the thermal stress across the buffer layer, the system can accommodate larger wafer sizes without experiencing the reliability failures that would otherwise limit substrate scale.
Solution Approach 2:
The patent modifies the thermal expansion parameter profile by introducing a buffer layer, which enables larger substrate wafer sizes to be used. The intermediate CTE of the buffer layer reduces thermal mismatch effects, allowing scaled-up production while maintaining device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CTE matching between the engineered substrate and the epitaxial layer reduces stress, improves device reliability, increases device density, and allows for more complex circuitry on larger substrates, while enabling the reuse of substrates, significantly lowering overall costs.
Implementation Method 1
the CTE of the engineered substrate substantially matches the CTE of the WBG epitaxial layer
Implementation Method 2
gallium nitride (GaN) materials may be formed by a heteropitaxial (epi) growth process that involves depositing GaN on a semiconductor carrier substrate
Data Source
AI summary
A method includes forming a wide band gap (WBG) epitaxial layer on an engineered substrate. The WBG epitaxial layer includes a plurality of groups of epitaxial layers. The engineered substrate includes engineered layers formed on a bulk material having a coefficient of thermal expansion (CTE) matching a CTE of the WBG epitaxial layer. The method also includes forming a plurality of WBG devices based on the plurality of groups of epitaxial layers by: for each respective WBG device, forming internal interconnects and electrodes within a respective group of epitaxial layers. The method further includes forming external interconnects between the electrodes of different WBG devices of the plurality of WBG devices to form an integrated circuit.