Widened Junction Transistor for Electro-Optical Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing electro-optical devices with LDD structure transistors face challenges in reducing leak current due to manufacturing complexities, which affect display quality and process yield.

Innovation Solution

The design includes a semiconductor film with a channel region, source/drain regions, and junction regions where at least one junction region has a wider width than the channel region, maintaining a concentration gradient to reduce leak current, and a light-shielding film to prevent light leaks, simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a sidewall is formed in a crescent shape or concave shape to reduce leak current, then leak current is reduced, but the manufacturing process becomes troublesome and yield deteriorates

Engineering Contradiction:
Improveleak currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention extracts the essential function of the sidewall (forming a concentration gradient to reduce leak current) and implements it through a simplified geometric configuration. Instead of complex crescent or concave sidewall shapes, the patent uses a straightforward widened junction region design that achieves the same electrolysis mitigation effect while being much easier to manufacture

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention inverts the conventional approach by not forming a sidewall at all, but rather by directly designing the junction region with a wider width than the channel region. This inverted approach achieves the same technical effect (reduced leak current through concentration gradient) while eliminating the manufacturing complexity associated with sidewall formation

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If complex sidewall processing is performed to reduce leak current, then transistor reliability improves, but manufacturing yield deteriorates

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidmanufacturing yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention changes the geometric parameter of the junction region by making its width larger than the channel region width. This parameter change creates the necessary concentration gradient for electrolysis mitigation, improving transistor reliability while avoiding complex processing steps that would reduce manufacturing yield

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leak current and improves display quality while simplifying the manufacturing process, enhancing the reliability and performance of electro-optical devices.

Implementation Method 1

By electrolysis mitigation effect based on the mutual impurity concentration gradient of the low-concentration impurity region and the high-concentration impurity region, leak current (that is, off-leak current) upon non-operation of the transistor is reduced

Methodology Applied
Scientific EffectElectrolysis mitigation effect:

Data Source

PatentUS8300170B2Electro-optical device, electronic apparatus, and transistor
Publication Date: 2012.10.30 138 EAST LCD ADVANCEMENTS LTD
  • US8300170B2 patent drawing
  • US8300170B2 patent drawing
  • US8300170B2 patent drawing

AI summary

An electro-optical device includes a substrate, a data line, and a transistor formed on the substrate and including (i) a semiconductor film having a channel region having a channel length according to one direction, first and second source/drain regions which are formed with the channel region interposed therebetween, and first and second junction regions respectively formed between the first and second source/drain region and the channel region, and (ii) a gate electrode overlapping with the channel region, wherein at least one of the first and second junction regions is formed such that the width thereof is at least partially larger than that of the channel region.