Wire Bond Sensor Package Height Reduction
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Solution Overview
Problem
Conventional chip packaging solutions, particularly those using wire bonding, face challenges in reducing package height to accommodate the trend towards slimmer mobile devices, as they cannot be scaled down effectively.
Innovation Solution
A packaged chip assembly is formed by securing a semiconductor chip to a second substrate with apertures and bond pads, allowing wires to pass through these apertures for electrical connection, and using a fan-out package structure with optimized bond wire loop height and modified die geometry to reduce overall package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional wire bonding packaging is used, then electrical connection between chip and substrate is achieved, but package height cannot be reduced to meet slim device requirements
Solution Approach 1:
The patent transitions from conventional top-surface wire bonding to a side-wall wire bonding configuration. Wires are bonded to the side walls of through-holes in the substrate rather than to surface pads, effectively utilizing the vertical dimension for electrical connection. This dimensional change allows for significantly reduced package height while maintaining reliable electrical connections between the chip and substrate.
Solution Approach 2:
The patent embeds wires within through-holes of the substrate, nesting the connection structure inside the substrate volume rather than having wires occupy external space. This nesting approach allows wires to pass through the substrate thickness, reducing the overall package height while maintaining electrical connectivity.
2Length of moving object
If package height is reduced for slim devices, then device thickness advantage is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent forms through-holes in the substrate before mounting the chip, preparing the bonding structure in advance. This preliminary action simplifies the overall manufacturing process by establishing the wire bonding pathways beforehand, reducing the complexity of subsequent assembly steps despite the innovative structure.
Data Source
AI summary
A packaged chip assembly with a semiconductor substrate, a semiconductor device integrally formed on or in the substrate's top surface, and first bond pads at the substrate's top surface electrically coupled to the semiconductor device. A second substrate includes a first aperture and one or more second apertures extending therethrough, second and third bond pads at the second substrate's top and bottom surfaces, respectively, and conductors electrically coupled to the second and third bond pads. The semiconductor substrate's top surface is secured to the second substrate's bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the second apertures. A plurality of wires are each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.