Wire-Structured Chip Capacitor for High Capacitance Miniaturization
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Solution Overview
Problem
Current chip capacitors occupy significant mounting area on wiring boards, limiting the miniaturization and integration density of high-performance electronic devices, and face challenges in achieving both high performance and reliability.
Innovation Solution
A chip capacitor design featuring a substrate with capacitor wires covered by a mold layer, where each wire includes a core electrode line, an outer electrode line, and a dielectric line, allowing for compact size reduction and enhanced electrostatic capacitance through wire bonding and stacking configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional chip capacitor structures are used, then mounting area is reduced, but integration density and performance are limited
Solution Approach 1:
The capacitor structure is segmented into multiple functional layers: core electrode line, dielectric line, and outer electrode line. This segmentation allows each component to be optimized independently while maintaining compact overall dimensions, thereby reducing mounting area without compromising integration density or reliability
Solution Approach 2:
The patent implements a nested structure where the dielectric line is positioned between the core electrode line and the outer electrode line. This nesting arrangement maximizes space utilization within the capacitor volume, enabling higher integration density while maintaining small mounting footprint
2Volume of moving object
If capacitor size is reduced for miniaturization, then mounting area decreases, but achieving high electrostatic capacitance becomes difficult
Solution Approach 1:
The patent employs a composite structure combining conductive materials (core electrode line, outer electrode line) with dielectric material (dielectric line). This composite arrangement enables high electrostatic capacitance within a reduced volume by optimizing the dielectric properties and electrode configuration
Solution Approach 2:
The patent transitions from planar electrode arrangements to a three-dimensional configuration with the dielectric line positioned between core and outer electrode lines. This dimensional change increases the effective capacitance area without proportionally increasing the capacitor's external dimensions, achieving high electrostatic capacitance in a compact size
3Reliability
If more capacitor components are added to improve performance, then electrostatic capacitance increases, but device complexity increases
Solution Approach 1:
The dielectric line serves multiple functions simultaneously: it provides electrical insulation between the core and outer electrode lines, contributes to the capacitance value, and maintains the structural integrity of the capacitor. This multi-functionality improves performance without proportionally increasing structural complexity
Solution Approach 2:
The patent merges the insulation function and capacitance-forming function into a single dielectric line component. By combining these functions in one element rather than using separate components, the design achieves high performance while maintaining relatively simple structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables easy scaling down of chip capacitors, increases integration density, and improves reliability by allowing for smaller sizes and higher electrostatic capacitance while maintaining high performance.
Implementation Method 1
Each of the capacitor wires may include a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line
Data Source
AI summary
A chip capacitor includes a substrate, a plurality of capacitor wires on the substrate, and a mold layer disposed on the substrate to cover the capacitor wires. Each of the capacitor wires includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.