Wire Tail Connector for Semiconductor Die
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Solution Overview
Problem
Conventional semiconductor packages have a larger footprint due to the need for space between die and wire bond positions on the substrate, which limits the compactness and efficiency of flash memory storage devices.
Innovation Solution
The solution involves forming bond wires between semiconductor die and anchor pads on the substrate, followed by encapsulation and singulation to expose and reconnect the bond wires, allowing for external connectors to electrically couple the die to the substrate, thereby reducing the overall size and enabling three-dimensional routing of electrical signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If wire bonds are formed close to the die on the substrate, then the substrate length and overall package length can be reduced, but the capillary will contact the die in the die stack before forming the bond on the substrate
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional wire bonding by routing wires over the side surfaces of the die stack. This dimensional change allows the wire bond capillary to access bond pads on vertical surfaces without contacting the top of the die, enabling shorter substrate lengths while maintaining reliable bond formation.
Solution Approach 2:
The patent applies preliminary protective coatings to the die surfaces before wire bonding. These coatings protect specific areas of the die from capillary contact during the bonding process, allowing the capillary to safely form bonds closer to the die without risking damage to the die structure.
2Reliability
If more space is provided between die and wire bond position on the substrate, then wire bond formation is reliable, but the overall package size increases
Solution Approach 1:
By moving wire bonding operations from the horizontal plane to vertical surfaces, the patent eliminates the need for large horizontal clearance between die and bond positions. The three-dimensional routing allows bonds to be formed on the side surfaces of the die stack, dramatically reducing the required package footprint while maintaining bonding reliability.
Solution Approach 2:
The patent nests the wire bonding process within the vertical profile of the die stack itself. Instead of requiring external horizontal space, the bonding operations are integrated into the three-dimensional structure of the stacked die, with wires routed along and around the die surfaces.
3Device complexity
If die are stacked with offset configuration, then wire bonding can be simplified, but the package width increases
Solution Approach 1:
The patent resolves the offset configuration issue by utilizing vertical and lateral surfaces of the die stack for wire routing. This three-dimensional approach allows wires to access bond pads on offset die without requiring additional package width, as the routing occurs along the vertical profile rather than expanding the horizontal footprint.
Data Source
AI summary
A memory device, and a method of making the memory device, are disclosed. The memory device is fabricated by mounting one or more semiconductor die on a substrate, and wire bonding the die to the substrate. The die and wire bonds are encapsuated, and the encapsulated device is singulated. The wire bonds are severed during the singulation step, and thereafter the severed wire bonds are connected to the substrate by external connectors on one or more surfaces of the molding compound.