Wireless IC Loopback Testing on Undiced Wafers

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Efficient testing of unpackaged integrated circuits (ICs) on a wafer is challenging due to the difficulty in building sockets and the area-intensive requirements of traditional testing methods, especially for ICs with radio-frequency content, making them impractical for many modern ICs.

Innovation Solution

The method involves transmitting signals between transmitter and receiver circuitry on the IC through a transmission line, allowing for loopback testing without the need for additional packaging, using existing transmitter and receiver circuitry to perform wireless data signal testing with low additional area and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Difficulty of detecting and measuring

If traditional probes are used for testing unpackaged ICs, then testing capability is achieved, but area requirements become excessively large and device complexity increases

Engineering Contradiction:
Improvetesting capabilityVSAvoidarea requirements
Core Design Contradiction:
Difficulty of detecting and measuringVSArea of stationary object

Solution Approach 1:

The patent merges the testing function with the existing transmitter and receiver circuitry of the IC. By using the IC's own communication components to perform self-testing through loopback paths, the solution eliminates the need for separate external probes and testing equipment, thereby reducing area requirements while maintaining testing capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The IC performs its own testing using its built-in transmitter and receiver circuitry. The device tests itself by transmitting signals through internal paths and receiving them back, eliminating the need for external testing apparatus and reducing both area requirements and device complexity

Inventive Principle:
Principle #25Self-service

2Difficulty of detecting and measuring

If traditional probes with companion ground lines are used, then signal transmission is supported, but the number of signal lines increases significantly

Engineering Contradiction:
Improvesignal transmission capabilityVSAvoidnumber of signal lines
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the need for companion ground lines and additional signal lines by using the IC's existing transmitter and receiver circuitry for testing. The loopback testing path uses only the necessary minimal lines already present in the IC design, significantly reducing the number of signal lines required

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The existing transmitter and receiver circuitry serves dual purposes: normal operation and self-testing. By making these components universal, the patent eliminates the need for separate dedicated testing lines and ground lines, reducing overall device complexity while maintaining full signal transmission capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7868639B1Methods and apparatus for integrated circuit loopback testing
Publication Date: 2011.01.11 MARVELL ASIA PTE LTD
  • US7868639B1 patent drawing
  • US7868639B1 patent drawing
  • US7868639B1 patent drawing

AI summary

Methods and apparatus are provided for performing loopback testing of integrated circuits (“ICs”). In an embodiment of the invention, an IC can be tested on an undiced wafer by coupling a wireless transmitter of the IC to a wireless receiver of the IC. Core circuitry of the IC can be controlled to cause the transmitter to send at least one signal to the receiver. Upon receipt of the at least one signal, the receiver can send a signal to the core circuitry, which can determine, and possibly record, whether the transmission and receipt were successful. The invention advantageously facilitates efficient testing of unpackaged ICs at the wafer level.