Wireless Aggregated Packet Forwarding Circuit for Lower Processor Load
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Solution Overview
Problem
The limited operating performance of network devices, particularly those with embedded systems, affects transmission rates and processor load due to the complexity of wireless network communication protocols like WiFi, making it challenging for devices with limited hardware resources to achieve maximum performance.
Innovation Solution
A method and circuit system for forwarding aggregated packets that includes a wireless network interface controller and driver, performing data frame conversion, aggregation, reordering, and de-aggregation to improve efficiency, while handling duplicate frames and adhering to a unified wireless local area network standard, with limits on aggregation quantity and length to manage resource constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If network devices operate embedded systems to handle wireless network packets, then the device can perform basic network functions, but the limited operating performance of the processor affects the transmission rate of network packets
Solution Approach 1:
The patent segments the packet processing function into two parts: a hardware circuit that performs aggregation and de-aggregation of packets, and a software processor that handles higher-layer forwarding. This segmentation offloads the time-consuming aggregation operations from the processor to the hardware circuit, reducing processor load and improving transmission rate.
Solution Approach 2:
The patent introduces a hardware circuit as an intermediary component between the wireless network interface and the processor. This circuit acts as a mediator that performs packet aggregation and de-aggregation operations, freeing the processor from these complex operations and improving overall system performance.
2Productivity
If the wireless network communication protocol complexity increases to support higher transmission rates, then the network can handle more data, but the processor load required for forwarding packets increases
Solution Approach 1:
The patent replaces the software-based packet aggregation mechanism with a hardware circuit implementation. This substitution moves the aggregation function from the software/mechanical domain to the hardware/electronic domain, enabling faster processing and reducing the computational burden on the processor.
3Productivity
If packet aggregation is performed to improve transmission efficiency, then fewer packets need to be processed, but the aggregation procedure requires additional processing resources and complexity
Solution Approach 1:
The patent merges the packet aggregation function into the hardware circuit, combining multiple packet processing operations (aggregation, de-aggregation, and forwarding) into a single integrated hardware component. This merging eliminates the need for separate software routines to handle aggregation, reducing overall system complexity while improving efficiency.
Data Source
AI summary
A method for forwarding aggregated packets and a circuit system are provided. In the method performed by the circuit system, after receiving multiple data frames, the data frames are converted to data frames with a unified wireless local area network standard. The header of the data frames is inserted with de-aggregation information so as to form subframes. In the meantime, an aggregation circuit is used to aggregate the multiple subframes so as to form multiple aggregated frames according to aggregation rules. Afterwards, a reorder procedure is performed on the aggregated frames based on sequence numbers of the aggregated frames, and the duplicate frames are also marked for a subsequent de-aggregation procedure to ignore the duplicate frames. The reordered aggregated frames are then outputted to a second-layer forwarding procedure in sequence for generating the packets to be forwarded after the aggregated frames are de-aggregated.