Wireless Receiver DC Offset Removal Without FIR HPF Distortion

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Solution Overview

Problem

Existing wireless receivers face a tradeoff between latency and signal quality when using finite impulse response high pass filters (FIR HPFs) to remove Direct Current Offset Components (DCOC) from intermediate frequency signals, as they cause gain and phase distortion, making it difficult to support multi-slot receivers efficiently.

Innovation Solution

A method and apparatus that utilize a hardware block, converter block, and digital signal processor (DSP) to efficiently remove DCOC from intermediate frequency signals before down conversion to baseband, generating parameters to estimate and eliminate residual DCOC, thereby minimizing latency and preserving signal spectrum with minimal distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a FIR HPF is used to remove DCOC from IF signal, then DCOC removal is achieved, but gain and phase distortion occurs degrading receiver performance

Engineering Contradiction:
Improvereceiver performanceVSAvoidgain and phase distortion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the DCOC component from the IF signal using a separate DCOC estimation and removal path, rather than using a FIR HPF that processes the entire signal. The DCOC is estimated by filtering the IF signal to extract only the DC component, then subtracting this estimated DCOC from the original IF signal, thereby removing the harmful DCOC without introducing gain and phase distortion to the signal spectrum.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The signal processing is segmented into distinct functional blocks: a DCOC estimation block that filters to extract DC component, a subtraction block that removes the estimated DCOC, and separate signal paths for I and Q components. This segmentation allows DCOC removal to be performed independently without affecting the signal spectrum characteristics.

Inventive Principle:
Principle #1Segmentation

2Reliability

If FIR HPF notch bandwidth is reduced to improve signal quality, then gain and phase distortion is minimized, but latency increases extending receiver setup time

Engineering Contradiction:
Improvesignal qualityVSAvoidreceiver setup time and latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The DCOC is extracted and removed separately from the signal path using a dedicated estimation and subtraction mechanism. This approach eliminates the need for a FIR HPF with its inherent latency, as the DCOC removal does not require long filter impulse responses. The receiver can achieve fast setup time while maintaining signal quality.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If FIR HPF is used for DCOC removal, then DCOC is reduced, but it becomes difficult to support multi-slot receiver due to extended latency

Engineering Contradiction:
ImproveDCOC removal effectivenessVSAvoidmulti-slot receiver support
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The DCOC removal function is extracted as a separate, independent processing path that does not impose latency constraints on the main signal processing. This enables the receiver to quickly acquire and process multiple slots without the setup time penalties associated with FIR HPF convergence, thereby supporting multi-slot operation effectively.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7593485B2Wireless receiver for removing direct current offset component
Publication Date: 2009.09.22 APPLE INC
  • US7593485B2 patent drawing
  • US7593485B2 patent drawing
  • US7593485B2 patent drawing

AI summary

A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.