Semiconductor Wiring Air Gap Spacer Structure
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Solution Overview
Problem
As semiconductor devices integrate more densely, the increased parasitic capacitance between wirings degrades their electrical characteristics, necessitating the development of wiring structures and manufacturing methods that reduce parasitic capacitance.
Innovation Solution
A method involving the formation of a wiring structure with air gaps by creating spacers of varying heights, where a first spacer has a top surface higher than the conductive pattern, a second spacer lower than the first spacer, and a third spacer contacting the first spacer to define an air gap, which reduces parasitic capacitance by incorporating a material with a low dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the space between wirings is decreased to increase integration degree, then device integration is improved, but parasitic capacitance between wirings increases
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent conductive patterns and replaces it with air gaps. By removing the solid dielectric and creating void spaces, the parasitic capacitance between closely spaced wirings is significantly reduced, allowing high integration without the harmful capacitive coupling effect
Solution Approach 2:
The patent introduces porous structures (air gaps) between conductive patterns to reduce parasitic capacitance. The air gaps act as low-dielectric constant regions that minimize electrical coupling between adjacent wirings while maintaining physical proximity for high integration density
2Reliability
If air gaps are formed between conductive patterns to reduce parasitic capacitance, then electrical characteristics are improved, but device structure becomes more complex
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial layers and spacers before finalizing the wiring structure. The first spacer is formed with a height higher than the conductive pattern, then a second spacer is formed on part of the first spacer, creating a structured template that defines where air gaps will be formed after sacrificial layer removal
Solution Approach 2:
The patent employs nested structures where the second spacer is formed on top of portions of the first spacer, and both are used to define the air gap regions. The spacers are nested in a hierarchical manner to create the complex three-dimensional air gap structure needed for parasitic capacitance reduction
3Object-generated harmful factors
If multiple spacers of varying heights are formed to define air gaps, then parasitic capacitance is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The patent segments the spacer formation into distinct stages: first spacer formation with height higher than conductive pattern, then second spacer formation on portions of the first spacer. This segmentation allows precise control of air gap dimensions and positions through separate deposition and etching processes
Solution Approach 2:
The patent uses sacrificial layers as intermediary materials that facilitate air gap formation. The sacrificial layers are deposited between the spacers, then selectively removed to create air gaps. This intermediary approach simplifies the manufacturing by providing a template-based method for creating complex void structures
Data Source
AI summary
A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer.