Wiring Board Warpage Suppression via Segmented Conductor Patterns

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Solution Overview

Problem

Wiring boards experience warpage due to differences in thermal expansion coefficients between insulating and wiring layers, leading to defects in soldering and housing fitment, and existing methods to suppress warpage are either inefficient or require extensive trial-and-error in optimizing conductor patterns.

Innovation Solution

A wiring board manufacturing method involving the formation of conductor patterns with zigzag or lattice patterns on the waste board section, where slits or through holes are strategically placed to balance the thermal expansion, reducing warpage by altering the residual copper rate and stiffness distribution across layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If conductor patterns are formed to balance thermal expansion, then warpage is suppressed, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvewarpage suppressionVSAvoidconductor pattern complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The conductor pattern is segmented into multiple polygonal lands arranged in a lattice structure, where each land is separated and connected through apex regions. This segmentation allows independent control of thermal expansion in different areas, enabling effective warpage suppression while maintaining manufacturability through standardized repeating units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conductor pattern implements local quality by creating regions with different copper densities - the apex regions have higher copper concentration while the land centers have lower concentration. This non-uniform distribution allows localized control of thermal expansion characteristics, balancing the overall board warpage while maintaining simple manufacturing processes.

Inventive Principle:
Principle #3Local quality

2Stability of the object's composition

If extensive trial-and-error is used to optimize conductor patterns, then warpage suppression improves, but manufacturing time and costs increase

Engineering Contradiction:
Improvewarpage suppressionVSAvoidpattern optimization time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The lattice-pattern conductor design is predetermined with fixed geometric parameters and arrangement rules that are calculated in advance to achieve optimal thermal balance. This preliminary design eliminates the need for extensive trial-and-error optimization during manufacturing, as the pattern structure itself is pre-configured to suppress warpage effectively.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention uses specific parameter relationships in the conductor pattern design - such as the area ratio between lands and apex regions, the spacing between adjacent lands, and the polygon shape characteristics - that are optimized beforehand. By fixing these parameters according to established design rules, the pattern achieves effective warpage suppression without requiring time-consuming iterative optimization.

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If the residual copper rate is altered to balance thermal expansion, then warpage is reduced, but the electrical conductivity may be affected

Engineering Contradiction:
Improvethermal expansion balanceVSAvoidelectrical conductivity
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The conductor pattern creates local quality variations where apex regions have high copper density for thermal balance while maintaining sufficient electrical connectivity, and land centers have lower copper density for thermal expansion control. The lattice structure ensures that electrical pathways are preserved through the apex connections while the overall copper distribution optimizes thermal characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The polygonal lands are designed with specific geometric shapes and the apex regions create curved connection paths that optimize both thermal and electrical performance. The geometric configuration ensures continuous electrical conductivity while the distributed apex regions provide the necessary copper density for thermal expansion balancing.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Effectively suppresses warpage across the wiring board, improving soldering reliability and housing fitment, while reducing the need for extensive pattern optimization, thus simplifying the manufacturing process and reducing costs.

Implementation Method 1

A wiring board with insulating layers and wiring layers alternately laminated may be warped due to a difference in the coefficient of thermal expansion between the insulating layer and the wiring layer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS10492291B2Wiring board manufacturing method
Publication Date: 2019.11.26 FUJITSU LTD
  • US10492291B2 patent drawing
  • US10492291B2 patent drawing
  • US10492291B2 patent drawing

AI summary

A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.