Wiring Board Warpage Suppression via Embedded Reinforcement
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Solution Overview
Problem
The challenge is to reduce the thickness of wiring boards incorporating semiconductor chips while minimizing warpage, as existing methods face difficulties in achieving both higher density and reduced thickness without structural lamination, which complicates the manufacturing process and reliability of connections.
Innovation Solution
A method involving the formation of a first and second insulating layer with a reinforcing member and semiconductor chip, where the reinforcing member is embedded in the insulating layer to suppress warpage, and a release layer facilitates peeling of the supporting board, allowing for heat curing and accurate via hole formation to enhance connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a laminated structure with a core board is used to suppress warpage, then warpage suppression is improved, but the thickness of the wiring board increases
Solution Approach 1:
The reinforcing member is positioned at a specific depth within the insulating layer rather than using a separate laminated core board structure. This dimensional integration allows warpage suppression without increasing overall board thickness, as the reinforcement is embedded within the existing layer structure.
Solution Approach 2:
The reinforcing member is nested within the insulating layer at a predetermined depth, creating a compact integrated structure. This nesting approach eliminates the need for separate laminated layers while maintaining warpage suppression functionality.
2Stability of the object's composition
If a laminated structure with a core board is used to suppress warpage, then warpage suppression is improved, but the manufacturing complexity increases
Solution Approach 1:
The reinforcing member and insulating layer are merged into a single integrated structure where the reinforcement is embedded within the insulating material. This combining of elements simplifies the manufacturing process by eliminating separate lamination steps and reducing structural complexity.
Solution Approach 2:
The reinforcing member is nested within the insulating layer, creating a unified structure that reduces manufacturing complexity compared to separate laminated layers.
3Length of stationary object
If the wiring board thickness is reduced, then higher density is improved, but warpage suppression becomes difficult
Solution Approach 1:
Instead of using thick laminated layers for warpage suppression, the solution embeds a reinforcing member at a specific depth within the insulating layer. This dimensional approach provides warpage control in a thin-profile structure.
Solution Approach 2:
The reinforcing member is positioned at a specific depth within the insulating layer where it is most effective for warpage suppression. This localized reinforcement provides optimal warpage control without requiring increased overall thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the thickness of the wiring board, suppresses warpage, and improves the reliability of connections between the wiring and semiconductor chip, while simplifying the manufacturing process and maintaining high flatness and reliability.
Implementation Method 1
curing the first insulating layer and the second insulating layer by heat, wherein the first insulating layer and the second insulating layer are made of heat-hardening resin material
Data Source
AI summary
A method of manufacturing a wiring board includes: forming a first insulating layer on a supporting board; mounting at least one reinforcing member on the first insulating layer; mounting at least one semiconductor chip on the first insulating layer; forming a second insulating layer on the reinforcing member and the semiconductor chip; and forming a wiring on the second insulating layer, the wiring being connected to the semiconductor chip.