Semiconductor Wiring Layout with Separated Sacrificial Sidewall Masks
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Solution Overview
Problem
Current side wall processing in semiconductor manufacturing faces limitations due to constraints on pattern shape formed by sacrificial layers, leading to unnecessary wiring patterns, short circuits, microloading effects, and dishing effects, which hinder the production of small-scale semiconductor devices with high yield and reliability.
Innovation Solution
The method involves forming insulation and conductive layers with sacrificial layers patterned to create functioning and dummy wiring areas, using these layers as masks to etch concavities and fill materials, while managing pattern density and spatial frequency to minimize microloading and dishing effects, and preventing short circuits by ensuring the sacrificial layers do not form a single connected component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If side wall processing is used to form detailed patterns beyond lithography resolution limits, then manufacturing precision is improved, but unnecessary wiring patterns and short circuits are generated
Solution Approach 1:
The patent segments the sacrificial layer into multiple independent regions (first sacrificial layer in functioning area, second sacrificial layer in dummy area) that are processed separately. This segmentation prevents the formation of connected components that would cause short circuits, while still enabling precise pattern formation through side wall processing in each independent region.
Solution Approach 2:
The patent applies different pattern density requirements to different areas: the functioning area uses sacrificial layers with controlled patterns for precise wiring formation, while the dummy area uses sacrificial layers specifically designed to adjust local pattern density. This local quality approach allows precise pattern formation where needed while preventing short circuits in other areas.
2Productivity
If wiring width is reduced to achieve small scale devices, then productivity is improved, but lithography resolution limits are exceeded
Solution Approach 1:
The patent uses preliminary action by first forming sacrificial layers with patterns that are larger than the final desired wiring dimensions. Then, through side wall processing, the actual wiring patterns are formed with precise dimensions that exceed lithography resolution limits. This preliminary sacrificial layer formation enables subsequent precise pattern definition without being constrained by lithography resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of small-scale semiconductor devices with reduced microloading and dishing effects, improved yield, and prevention of short circuits, allowing for more precise pattern formation beyond lithography resolution limits.
Implementation Method 1
forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask
Data Source
AI summary
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.