Wiring Structure With Intermediate Layer For Warpage Control
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Solution Overview
Problem
The increasing number of input/output (I/O) connections in semiconductor chips leads to larger and thicker semiconductor substrates, resulting in reduced yield and warpage issues, which are not effectively addressed by existing manufacturing methods.
Innovation Solution
A wiring structure comprising an upper conductive structure, a lower conductive structure, and an intermediate layer, where the upper conductive structure has a high-density circuit layer with a low line width/line space, and the lower conductive structure has a low-density circuit layer without glass fiber, bonded together by an intermediate layer with a controlled coefficient of thermal expansion, optimizing yield and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/O connections is increased, then the electrical performance and functions are improved, but the substrate size and thickness increase, resulting in reduced yield and warpage
Solution Approach 1:
The patent divides the substrate into multiple layers (first substrate, second substrate, intermediate layer) to segment the I/O connections. This allows increasing the number of I/O connections without proportionally increasing the overall substrate thickness, as connections are distributed across layers rather than confined to a single thick substrate.
Solution Approach 2:
The patent transitions from a two-dimensional planar connection architecture to a three-dimensional stacked architecture. By adding the intermediate layer and creating vertical interconnections, the design utilizes the third dimension (thickness direction) to accommodate additional I/O connections without increasing the lateral substrate size, thereby maintaining manufacturing precision and yield.
2Adaptability or versatility
If the substrate thickness is increased to accommodate more I/O connections, then the electrical performance is improved, but the warpage increases and yield decreases
Solution Approach 1:
The patent changes the material parameter of the intermediate layer by selecting a material with a coefficient of thermal expansion (CTE) that is intermediate between the first and second substrates. This parameter adjustment allows the intermediate layer to act as a buffer that compensates for thermal expansion differences, reducing warpage while maintaining the stacked structure for high I/O connectivity.
Solution Approach 2:
The patent employs a composite structure consisting of different materials (first substrate, intermediate layer, second substrate) with different CTE values. This composite architecture allows each layer to contribute its specific properties, with the intermediate layer specifically designed to mitigate warpage through its intermediate CTE value, while the overall structure achieves high I/O connection density.
3Strength
If glass fiber is added to the dielectric layer, then the structural strength is improved, but the CTE mismatch increases causing warpage
Solution Approach 1:
The patent changes the CTE parameter of the dielectric layer by replacing or reducing glass fiber content with alternative materials having CTE values better matched to the surrounding structures. This parameter adjustment reduces CTE mismatch and resulting warpage while maintaining sufficient structural strength through the overall stacked design.
Solution Approach 2:
The patent applies different material compositions to different regions and layers. The intermediate layer and specific dielectric layers are designed with tailored material properties (lower glass fiber content, different CTE values) to locally address warpage issues in critical regions, while other areas maintain structural strength requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves manufacturing yield and reduces warpage by separating the warpage effects of the upper and lower conductive structures, achieving a balance between yield and cost while maintaining a relatively low thickness.
Implementation Method 1
a coefficient of thermal expansion (CTE) of the upper conductive structure is less than a CTE of the intermediate layer, and the CTE of the intermediate layer is less than a CTE of the lower conductive structure
Data Source
AI summary
A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.