Wiring Substrate with Composite Seed Layer for Glass Core
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Solution Overview
Problem
Existing wiring substrates face challenges in achieving high-quality conductor circuits on glass substrates due to issues with thermal expansion coefficient differences and peeling of conductive layers, leading to potential cracks and reduced reliability.
Innovation Solution
A wiring substrate design featuring a glass core substrate with through-hole conductors, a seed layer, and an electrolytic plating layer, where the conductor layer is formed with a specific width configuration and recessed sidewalls to mitigate stress and enhance bonding, using a copper alloy seed layer and copper electrolytic plating layer, and resin insulating layers with inorganic particles for improved flatness and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional conductor layer is formed on a glass substrate, then conductor circuits can be created, but thermal expansion coefficient differences cause peeling and cracks reducing reliability
Solution Approach 1:
The patent applies composite materials by forming a copper alloy seed layer (containing elements like Ni, Pd, Pt, Ag, or Au) followed by a copper electrolytic plating layer. This multi-layer composite structure combines the adhesion benefits of the copper alloy seed layer with the conductivity and mechanical stability of the copper plating layer, resolving the bonding strength issue between the conductor layer and glass substrate while maintaining electrical performance and reliability.
2Strength
If the conductor layer width is increased to improve bonding, then adhesion improves, but stress transmission increases causing cracks
Solution Approach 1:
The patent applies local quality by creating a multi-layer conductor structure where the copper alloy seed layer provides localized adhesion enhancement at the interface with the glass substrate, while the copper electrolytic plating layer provides localized conductivity and stress distribution. This localized differentiation of material properties allows the conductor layer to bond strongly without transmitting excessive stress to the substrate, preventing crack formation.
3Reliability
If a thick conductor layer is formed to reduce peeling, then bonding improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses composite materials with a copper alloy seed layer and copper electrolytic plating layer, where the seed layer thickness is controlled at 1-10 μm and the plating layer thickness is controlled at 10-50 μm. This composite approach provides effective peeling resistance through the adhesion-promoting seed layer while keeping the overall structure manageable and manufacturable, avoiding excessive complexity.
Solution Approach 2:
The patent applies parameter changes by precisely controlling the thickness parameters of the seed layer (1-10 μm) and electrolytic plating layer (10-50 μm), as well as the composition parameters of the copper alloy seed layer. These optimized parameter ranges achieve reliable peeling resistance while maintaining manufacturing feasibility and avoiding unnecessary structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves stable and reliable conductor circuits with reduced stress transmission and peeling risks, allowing for fine wiring formation and improved electrical signal propagation without significant noise or delay.
Implementation Method 1
an electrolytic plating layer formed on the seed layer
Data Source
AI summary
A wiring substrate includes a core substrate including a through-hole conductor, a first resin insulating layer, a first conductor layer including a seed layer and an electrolytic plating layer, a via conductor formed such that the via conductor electrically connects the through-hole conductor and first conductor layer, and a second resin insulating layer covering the first conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is penetrating through the glass substrate, the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, and the first conductor layer includes a conductor circuit such that a width of the first layer is larger than a width of the second layer in the conductor circuit and a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.