Wiring Substrate Miniaturized Pads Electroless Plating
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Solution Overview
Problem
As semiconductor devices become more integrated, there is a need for miniaturization of pads on wiring substrates to accommodate increased complexity and density without compromising accuracy and yield in manufacturing.
Innovation Solution
A wiring substrate design featuring miniaturized pads formed by electroless plating within via holes in the insulating layer, with a gold-palladium-nickel film stack for the first pads and electrolytic copper plating for the second pads, connected through via conductors, allowing for precise alignment and formation without the need for a plating resist layer, enabling high-accuracy microfabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads are miniaturized to increase integration density, then the integration density is improved, but the manufacturing precision and yield deteriorate
Solution Approach 1:
The patent replaces the conventional mechanical/photoresist-based pad formation process with an electroless plating process. Instead of using plating resist layers and complex alignment procedures, the invention forms pads through electroless plating on the bottom surface of via holes, eliminating mechanical alignment constraints and enabling precise miniaturized pad formation at scale
Solution Approach 2:
The patent changes the fundamental parameter of pad formation from a mechanical deposition process to a chemical electroless plating process. This parameter change enables controlled metal deposition directly in via holes without requiring resist patterns, thereby maintaining manufacturing precision while achieving miniaturization
2Quantity of substance
If pads are miniaturized to increase integration density, then the integration density is improved, but the manufacturing complexity and yield loss increase
Solution Approach 1:
The patent extracts and eliminates the plating resist layer from the conventional pad formation process. By removing this unnecessary component, the invention simplifies the manufacturing process, reduces the number of steps required, and eliminates associated complexity while still achieving miniaturized pad formation with high precision
Solution Approach 2:
The electroless plating process is self-aligning, automatically forming pads at the via hole locations without requiring external alignment mechanisms or resist patterns. This self-service characteristic eliminates complex alignment procedures and reduces manufacturing complexity while enabling miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the miniaturization of pads on wiring substrates and semiconductor devices, enhancing integration density while maintaining high accuracy and reducing manufacturing yield loss, enabling efficient flip chip bonding and wire bonding.
Implementation Method 1
forming a pad on the support substrate exposed in the via hole by electroless plating
Implementation Method 2
electrolytic copper plating for the second pads
Data Source
AI summary
A wiring substrate includes an insulating layer, a pad in a via hole piercing through the insulating layer and exposed at a first surface of the insulating layer, a via conductor on the pad in the via hole, and a wiring part on a second surface of the insulating layer facing away from the first surface. The wiring part is connected to the pad through the via conductor in the via hole.