Wiring Substrate Passive Devices Parasite Capacity Reduction

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Solution Overview

Problem

Multi-chip modules (MCMs) face challenges in miniaturization and performance due to conflicting requirements for dielectric materials, which affect the placement and integration of passive components like capacitors and inductors, leading to insufficient size reduction and performance issues.

Innovation Solution

The integration of passive devices directly formed on the wiring substrate using micromachining technology, eliminating the need for large surface-mountable components and dielectric material between them, allowing for reduced parasite capacities and increased freedom in selecting high dielectric materials, along with three-dimensional wiring for flexible component connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If passive parts are placed inside the wiring substrate, then size reduction is achieved, but parasite capacities increase and Q factor decreases

Engineering Contradiction:
Improvemodule sizeVSAvoidparasite capacity
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the harmful dielectric material from between passive devices and wires by creating voids or air gaps in the wiring substrate. This removes the source of parasite capacities while maintaining the compact integrated structure, directly resolving the contradiction between size reduction and parasite capacity reduction.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The wiring substrate is designed with porous or void-containing structures where dielectric material is intentionally omitted from specific regions. These porous regions serve as air gaps that eliminate parasite capacities between passive devices and wiring, enabling both compact integration and high Q factor performance.

Inventive Principle:
Principle #31Porous materials

2Quantity of substance

If a high dielectric constant material is used in the wiring substrate, then capacitor electrostatic capacity increases, but inductor Q factor decreases

Engineering Contradiction:
Improveelectrostatic capacityVSAvoidinductor Q factor
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies different dielectric properties to different locations within the wiring substrate. High dielectric constant material is used in capacitor regions to maximize electrostatic capacity, while voids or air gaps are created in inductor and wire regions to minimize parasite capacities and maintain high Q factor. This localized differentiation resolves the contradiction between capacitor performance and inductor performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The wiring substrate is segmented into function-specific regions with different dielectric characteristics. Capacitor areas utilize high dielectric constant material for maximum capacity, while inductor and wiring areas utilize air gaps or low dielectric constant regions. This segmentation allows each component type to operate under optimal dielectric conditions simultaneously.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8345438B2Electronic part module and method of making the same
Publication Date: 2013.01.01 TAIYO YUDEN KK
  • US8345438B2 patent drawing
  • US8345438B2 patent drawing
  • US8345438B2 patent drawing

AI summary

An electronic part module includes a wiring substrate, a passive device group of passive devices formed on the wiring substrate, and device chips mounted on the wiring substrate. Such an electronic part module is made in the following manner. First, a wiring substrate wafer is made, to include a plurality of electronic part module formation areas. Then, a plurality of passive devices are formed in each of the electronic part module formation areas on the wiring substrate wafer. Then, the device chips are formed on each of the electronic part module formation areas on the wiring substrate wafer. Finally, the wiring substrate wafer is divided.