Wiring Substrate Recessed Plating Layer Design
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Solution Overview
Problem
The formation of solder bumps on wiring substrates is time-consuming and reduces yield, as it requires additional processing steps and can be inefficient.
Innovation Solution
A wiring substrate design featuring a first plating layer recessed on the outer surface of the first insulating layer and a second plating layer either flush or protruding from the second insulating layer, eliminating the need for conventional solder bumps by forming electroless Ni/Pd/Au metal layers on conductor pads, which are integrated into the substrate manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are formed on conductor pads, then electrical connection is achieved, but manufacturing time increases and yield decreases
Solution Approach 1:
The patent extracts the solder bump formation step from the manufacturing process by using electroless plating layers (Ni/Pd/Au) that are formed simultaneously with the conductor layers during PCB fabrication. This eliminates the need for separate solder bump formation steps, thereby improving yield while maintaining electrical connection functionality.
Solution Approach 2:
The electroless plating layers are formed in advance during the PCB manufacturing process, before the wiring substrate is assembled. The conductor pads are pre-coated with Ni/Pd/Au layers, so that when the substrate is assembled, the electrical connection is already established without requiring additional solder bump formation steps.
2Reliability
If solder bumps are formed on conductor pads, then electrical connection is achieved, but additional processing steps are required
Solution Approach 1:
The patent merges the conductor layer formation and plating layer formation into a single integrated process. The electroless plating layers (Ni/Pd/Au) are deposited simultaneously with the conductor copper layers during PCB fabrication, combining multiple steps into one unified manufacturing process and eliminating separate solder bump formation steps.
Solution Approach 2:
The electroless plating layers serve multiple functions: they act as conductor layers for electrical connection, provide corrosion resistance, and eliminate the need for separate solder bumps. This multi-functionality reduces the number of processing steps while maintaining reliable electrical connection.
3Productivity
If electroless plating layers are formed on conductor pads, then manufacturing efficiency is improved, but plating uniformity must be maintained
Solution Approach 1:
The patent uses electroless plating technology which allows for uniform deposition of Ni/Pd/Au layers through controlled chemical reactions. By adjusting plating solution composition, temperature, and deposition time, uniform plating thickness can be achieved across all conductor pads simultaneously, maintaining manufacturing precision while improving efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances yield by simplifying the mounting process and allowing for compact electronic circuit arrangements without the need for additional solder bumps, while using the same electroless plating treatment for both types of plating layers.
Implementation Method 1
an electroless plating layer may be formed on a conductor pad
Data Source
AI summary
A wiring substrate includes a first outermost conductor layer, a first outermost insulating layer covering the first conductor layer, a second outermost conductor layer formed on opposite side of the first conductor layer, and a second outermost insulating layer covering the second conductor layer. The first insulating layer has first openings such that the first openings are exposing first conductor pads including portions of the first conductor layer, the second insulating layer has second openings such that the second openings are exposing second conductor pads including portions of the second conductor layer, each of the first conductor pads has a first plating layer recessed with respect to outer surface of the first insulating layer, and each of the second conductor pads has a second plating layer formed flush with outer surface of the second insulating layer or having bump shape protruding from the outer surface of the second insulating layer.