Wiring Substrate with 3 μm Surface Layer
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Solution Overview
Problem
Current wiring substrates face challenges in achieving high-density, reliable, and defect-free wiring configurations with fine wiring widths and small inter-wiring distances, particularly in surface-layer parts, which affect signal transmission quality and reliability.
Innovation Solution
The proposed wiring substrate structure includes a core substrate with alternating insulating and conductor layers, featuring a third build-up part with conductor layers having a minimum wiring width and inter-wiring distance of 3 μm or less and an aspect ratio between 2.0 and 4.0, along with a fourth build-up part with a single or multiple conductor layers, optimized for high-density surface-layer wiring with reduced defects and improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the wiring width and inter-wiring distance are reduced to increase wiring density, then the wiring density is improved, but the manufacturing precision and reliability deteriorate due to difficulty in forming fine patterns and increased defect rates
Solution Approach 1:
The build-up layers are divided into multiple sub-layers (first build-up layer with first and second conductor layers, second build-up layer with third and fourth conductor layers). This segmentation allows progressive formation of fine patterns through multiple lithography and etching steps, where each step works on a manageable pattern size while contributing to the final high-density configuration.
Solution Approach 2:
Coating layers are formed on the surface of each build-up layer before pattern formation. These coating layers serve as protective and preparatory structures that facilitate subsequent fine pattern formation processes, enabling precise patterning at 3 μm or less wiring width by providing a controlled surface for lithography and etching operations.
2Quantity of substance
If the aspect ratio of wirings is increased to achieve higher wiring density, then the wiring density is improved, but the reliability deteriorates due to increased signal insertion loss and defect formation
Solution Approach 1:
Different build-up layers are designed with different wiring configurations. The first and second conductor layers have different wiring widths and pitch dimensions, allowing optimization of signal transmission paths. High-aspect-ratio wirings (3.0 or more) are strategically placed where high density is needed, while other areas maintain lower aspect ratios for better signal integrity.
Solution Approach 2:
The patent utilizes multiple stacked conductor layers (first, second, third, and fourth conductor layers) to distribute wiring functions across different vertical dimensions. This reduces the burden on any single layer, allowing high-density routing without excessively increasing the aspect ratio of individual wirings, thereby maintaining signal transmission reliability.
3Quantity of substance
If fine wirings with small wiring width and inter-wiring distance are formed, then the wiring density is improved, but the reliability worsens due to increased defect formation and signal insertion loss
Solution Approach 1:
Coating layers are formed beforehand on each build-up layer to protect the underlying structures during subsequent processing steps. These coating layers act as cushioning elements that prevent defect formation during lithography, etching, and handling processes, ensuring that fine patterns with 3 μm or less wiring width are formed without excessive defects.
Solution Approach 2:
The patent specifies precise parameter ranges for wiring dimensions (3 μm or less wiring width, 3 μm or less inter-wiring distance, aspect ratio of 2.0 or more) and uses these controlled parameters to achieve high density while maintaining reliability. The systematic control of these parameters across multiple conductor layers ensures consistent quality.
Data Source
AI summary
A wiring substrate includes a core substrate; a first build-up part including first conductor layers, a second build-up part including second conductor layers, a third build-up part including third conductor layers and having the outermost surface of the wiring substrate, and a fourth build-up part including one or more fourth conductor layers and having the outermost surface of the wiring substrate. The minimum wiring width of wirings in the third conductor layers is smaller than that of wirings in the first, second and fourth conductor layers. The minimum inter-wiring distance of the wirings in the third conductor layers is smaller than that of the wirings in the first, second and fourth conductor layers. The wirings in the third conductor layers have the minimum wiring width of 3 μm or less, the minimum inter-wiring distance of 3 μm or less, and an aspect ratio in the range of 2.0 to 4.0.