Wiring Substrate Via Structure Thermal Stress Management
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Solution Overview
Problem
In high-density semiconductor devices with stacked via structures, thermal stress concentrates at the lowermost part, leading to via destruction and unreliable electrical connections, especially when the stack number of vias increases, and existing methods struggle to ensure reliable connections between semiconductor chips and wiring substrates with varying electrode pad structures.
Innovation Solution
A wiring substrate design featuring a first multi-layer wiring layer with a stacked via structure and a second multi-layer wiring layer with a non-stacked via structure, where the second electrode pad is formed on the uppermost insulating layer, and the first electrode pad is exposed on the second insulating layer, positioned one layer lower, allowing for reduced via stacking and minimized level differences between regions, enabling reliable connections through optimized solder layer adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked via structure is used to achieve higher density mounting, then the mounting density is improved, but thermal stress concentrates at the lowermost part causing via destruction
Solution Approach 1:
The patent divides the via structure into two types: stacked vias in the first multi-layer wiring layer and non-stacked vias in the second multi-layer wiring layer. This segmentation allows the design to maintain high density where stacked vias are used while avoiding via destruction in critical areas by using non-stacked vias with electrode pads exposed on the insulating layer surface, thereby distributing thermal stress more effectively.
Solution Approach 2:
The patent applies different via structures to different regions: stacked vias are used in the first multi-layer wiring layer for general high-density requirements, while non-stacked vias with exposed electrode pads are used in the second multi-layer wiring layer for critical connections where thermal stress resistance is paramount. This local differentiation optimizes both density and reliability in respective zones.
2Productivity
If the stack number of vias is increased to achieve higher density, then the mounting density is improved, but via destruction occurs more easily due to stress concentration
Solution Approach 1:
The patent extracts the problematic stacked via structure from the second multi-layer wiring layer and replaces it with non-stacked vias where electrode pads are formed directly on the insulating layer. This removal of stacked vias in critical areas eliminates the thermal stress concentration mechanism while maintaining overall high density through the first multi-layer wiring layer's stacked via structure.
3Reliability
If different via structures are used in different wiring layers, then via destruction risk is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent merges the advantages of both stacked and non-stacked via structures within a unified multi-layer wiring system. The first multi-layer wiring layer uses stacked vias for density, while the second multi-layer wiring layer uses non-stacked vias for reliability, creating a combined structure that achieves both high density and high reliability without requiring entirely separate designs.
Data Source
AI summary
A wiring substrate includes a first multi-layer wiring layer having a stacked via structure including a first electrode pad, a second multi-layer wiring layer having a non-stacked via structure including a second electrode pad. The second electrode pad is formed on an uppermost first insulating layer. The first electrode pad is formed on a second insulating layer which is located to a position lower by one layer than the first insulating layer, and the first electrode pad is arranged in an opening portion of the first insulating layer such that the upper face and the side face of the first electrode pad are exposed.