Wafer Level Chip Scale Package Copper Post Interconnects
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Solution Overview
Problem
Current Wafer Level Chip Scale Packages (WLCSP) cannot be directly embedded into a substrate due to solder material melting issues during reflow, leading to reliability problems, and they lack high current carrying capacity and electromagnetic shielding.
Innovation Solution
A WLCSP structure is developed with copper posts instead of solder balls, embedded in a substrate, featuring a silicon die on a metal substrate with metal vias and a lamination layer, and a process involving redistribution layers, passivation, seed layer deposition, copper plating, and laser drilling for via formation, enabling high current carrying capacity and electromagnetic shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If solder balls are used for interconnections in WLCSP, then the package can be manufactured with conventional processes, but the solder material melts during reflow and causes reliability issues when embedded in substrate
Solution Approach 1:
The patent changes the material parameter from solder ball to copper post interconnection structure. This fundamental material substitution eliminates the melting issue during reflow while maintaining manufacturability through established copper plating and substrate embedding processes
Solution Approach 2:
The patent extracts the spherical solder ball component from the interconnection structure and replaces it with copper posts that are directly formed on the die surface. This extraction removes the problematic melting characteristic while preserving the electrical interconnection function
2Ease of manufacture
If solder balls are used for interconnections, then the manufacturing process is simpler, but the current carrying capacity and electromagnetic shielding are insufficient
Solution Approach 1:
The patent changes the interconnection material from solder to copper, which has superior electrical conductivity and current carrying capacity. The copper post structure provides enhanced electromagnetic shielding while maintaining a relatively simple manufacturing process through standard semiconductor fabrication techniques
Solution Approach 2:
The patent employs a composite interconnection structure consisting of copper posts embedded in the substrate, combining the high conductivity of copper with the mechanical support and shielding capabilities of the substrate material, thereby achieving both high current carrying capacity and electromagnetic shielding
3Reliability
If WLCSP is embedded in substrate with copper posts, then high current carrying capacity and electromagnetic shielding are achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the interconnection structure into distinct functional components: copper posts for electrical connection, lamination layer for embedding, and metal vias for through-substrate connectivity. This segmentation allows each component to be optimized independently while maintaining overall process feasibility
Solution Approach 2:
The patent performs preliminary actions by forming copper posts on the die surface before substrate embedding, and creating metal vias through the substrate before final lamination. These preliminary structures simplify the subsequent assembly process and ensure proper alignment and connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for the embedding of WLCSP into a substrate with improved electrical performance, heat dissipation, and cost savings by eliminating solder balls, while providing high current carrying capability and electromagnetic shielding.
Implementation Method 1
Copper is plated on the seed layer in the first and second openings to form copper posts filling the second openings
Implementation Method 2
Third openings are formed through the lamination layer to the copper posts and to metal pads on the metal substrate
Data Source
AI summary
At least one redistribution layer (RDL) is provided on a silicon die. A passivation layer is deposited on the RDL. First openings having a first diameter are etched in the passivation layer where copper posts are to be formed. A seed layer is deposited over the passivation layer and within the openings. A photoresist layer is coated on the seed layer and patterned to form second openings having a second diameter over the first openings larger than the first diameter. Copper is plated on the seed layer to form copper posts filling the second openings. The silicon die is die attached to a metal substrate. A lamination layer is coated over the silicon die and the copper posts. Third openings are formed through the lamination layer to the copper posts and to metal pads on the metal substrate. Metal vias are formed in the third openings.