CTE-Matched Encapsulant for WLCSP Thermal Stress

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Solution Overview

Problem

Large array wafer level chip scale packages (WLCSP) and fan-out WLCSP mounted on printed circuit boards (PCBs) experience failures and reduced board level reliability due to thermal expansion mismatches between the PCB and the semiconductor packages, leading to stress-induced issues during temperature cycling testing.

Innovation Solution

A method involving the formation of a cavity in a substrate with an encapsulant or stress compensating structure having a coefficient of thermal expansion (CTE) similar to the semiconductor package, followed by the deposition of an insulating layer and a conductive layer, allowing for the mounting of a semiconductor package with reduced thermal stress by matching the CTE of the encapsulant or stress compensating structure to the package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If large array WLCSP/FO-WLCSP are mounted on PCB, then signal processing capacity is improved, but board level reliability deteriorates due to CTE mismatch stress

Engineering Contradiction:

Improvesignal processing capacityVSAvoidboard level reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces an intermediary layer (encapsulant or stress compensating structure) between the semiconductor package and PCB substrate. This intermediary has a CTE value that is intermediate between the package and substrate, acting as a buffer to reduce thermal stress while maintaining the electrical functionality of the large array package.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical parameter (CTE) of the material between the package and substrate by selecting encapsulant or stress compensating structures with specific CTE values that match or are intermediate to both components, thereby resolving the thermal expansion mismatch problem.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If encapsulant or stress compensating structure with matched CTE is added, then thermal stress is reduced, but device complexity increases

Engineering Contradiction:

Improvethermal stress reductionVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the encapsulant serve multiple functions: it provides the traditional protective encapsulation function while simultaneously acting as a stress compensating structure due to its matched CTE. This multi-functionality reduces the need for separate stress compensation components, thereby limiting the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If CTE-matched encapsulant is used, then stress between package and substrate is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improvestress reductionVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent performs preliminary action by pre-matching the CTE of the encapsulant material to the semiconductor package before mounting. The encapsulant is selected and prepared with the appropriate CTE properties in advance, so that when the package is mounted, the stress compensation occurs automatically without requiring additional manufacturing steps or adjustments.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces stress between the semiconductor package and the substrate, enhancing the reliability of the semiconductor device by minimizing thermal expansion mismatches, thereby reducing failures during temperature cycling testing.

Implementation Method 1

The CTE of the encapsulant is selected similar to the CTE of the semiconductor package to reduce stress between the semiconductor package and substrate

Methodology Applied

Scientific EffectCoefficient of thermal expansion (CTE): Thermal Expansion

Data Source

PatentUS8895358B2Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP

Publication Date: 2014.11.25 STATS CHIPPAC LTD

AI summary

A semiconductor device has a PCB with a cavity formed in a first surface of the PCB. A stress compensating structure, such as an encapsulant or dummy die, is disposed in the cavity. An insulating layer is formed over the PCB and stress compensating structure. A portion of the insulating layer is removed to expose the stress compensating structure. A conductive layer is formed over the stress compensating structure. A solder masking layer is formed over the conductive layer with openings to the conductive layer. A semiconductor package is mounted over the cavity. The semiconductor package is a large array WLCSP. Bumps electrically connect the semiconductor package and conductive layer. The semiconductor package is electrically connected to the conductive layer. The CTE of the stress compensating structure is selected substantially similar to or matching the CTE of the semiconductor package to reduce stress between the semiconductor package and PCB.