WLCSP Interconnect Structure Embedding Semiconductor Component
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Solution Overview
Problem
Conventional fan-out wafer level chip scale packages (FO-WLCSP) experience reduced operating speed due to long signal paths through build-up interconnect layers and through silicon/through hole vias, and suffer from manufacturing inefficiencies and increased costs due to unnecessary material usage and gaps between semiconductor die and build-up layers.
Innovation Solution
A method of forming a semiconductor device with a semiconductor die, an encapsulant, an insulating layer, and interconnect structures to embed a semiconductor component, reducing gaps and material usage by forming conductive bumps and redistribution layers for efficient signal routing and embedding semiconductor die in build-up layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional fan-out wafer level chip scale packages (FO-WLCSP) are used with build-up interconnect layers, then structural support and electrical interconnection are provided, but signal path length increases reducing operating speed
Solution Approach 1:
The patent transitions from planar routing of signals through build-up interconnect layers to three-dimensional vertical routing through TSVs (through-silicon vias). This dimensional change allows signals to travel directly between stacked semiconductor dies through the vertical dimension, dramatically reducing signal path length and improving operating speed while maintaining electrical interconnection functionality.
2Ease of manufacture
If build-up interconnect layers are formed across each semiconductor die, then electrical interconnection is achieved, but manufacturing materials and cost increase unnecessarily
Solution Approach 1:
The patent extracts and eliminates the unnecessary build-up interconnect layers from the conventional FO-WLCSP structure. By removing these layers and replacing them with TSV-based vertical interconnection, the invention reduces manufacturing materials and costs while maintaining the essential electrical interconnection functionality between semiconductor dies.
Solution Approach 2:
Instead of forming interconnect layers across the entire semiconductor die surface, the patent applies interconnect structures only in specific local areas where electrical connection is needed. This localized approach reduces unnecessary material usage while achieving the required electrical interconnection functionality.
3Strength
If conventional packaging processes are used, then structural support is provided, but gaps and space are formed between semiconductor die and build-up layers reducing reliability
Solution Approach 1:
The patent applies underfill material in advance between the semiconductor die and the substrate before final packaging. This underfill material fills gaps and provides mechanical cushioning and stress relief, preventing reliability issues that would arise from gaps between components. The cushioning is provided beforehand to ensure structural integrity and reliability throughout the device lifecycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances reliability and operating speed by reducing signal path length and eliminating the need for underfill materials, while improving manufacturing efficiency and reducing costs by minimizing unnecessary material usage and gaps between semiconductor die and build-up layers.
Implementation Method 1
depositing an encapsulant over the semiconductor die
Implementation Method 2
forming a first interconnect structure over the encapsulant and first surface of the semiconductor die to embed the semiconductor component
Data Source
AI summary
A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.