WLCSP Interposer Structure for Thin Package Integration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces limitations in reducing the total thickness of package-on-package (PoP) technology due to constraints in solder ball joint height and pitch, which hinders further integration density and miniaturization of electronic components.

Innovation Solution

A wafer level chip scale packaging (WLCSP) intermediate structure is developed, involving a carrier wafer with a redistribution layer (RDL) and interposer dies, where a molding compound and underfill are used to support interposer dies, and additional RDLs are formed to enable efficient electrical connectivity and reduce package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If solder ball joint height and pitch are reduced to achieve thinner PoP packages, then package thickness is reduced, but integration density and miniaturization are hindered

Engineering Contradiction:
Improvepackage thicknessVSAvoidintegration density
Core Design Contradiction:
Length of stationary objectVSProductivity

Solution Approach 1:

An intermediate structure is introduced between the first and second packages in the PoP configuration. This intermediate structure includes a carrier substrate with redistribution layers (RDLs) that provide electrical connections between the packages. The intermediate structure acts as a mediator that enables thinner package profiles by redistributing connection points and eliminating the need for tall solder ball joints, thereby resolving the contradiction between reduced thickness and maintained integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transitions from vertical stacking with direct solder ball connections to a configuration using intermediate redistribution layers that extend electrical connections in lateral dimensions. The RDLs on the intermediate structure substrate create additional connection pathways in the horizontal plane, allowing the package thickness to be reduced while maintaining electrical connectivity and integration density through dimensional redistribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If solder ball joint height is reduced to achieve lower package profile, then package thickness is reduced, but distance between adjacent joints (pitch) becomes constrained

Engineering Contradiction:
Improvepackage thicknessVSAvoidpitch between joints
Core Design Contradiction:
Length of stationary objectVSLength of moving object

Solution Approach 1:

The intermediate structure with its carrier substrate and redistribution layers serves as a mediator that decouples the relationship between package thickness and joint pitch. By introducing this intermediate layer, the patent enables independent optimization of vertical thickness and horizontal pitch dimensions, as the RDLs provide flexible electrical pathways that are not constrained by traditional solder ball geometry.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The connection structure is segmented into multiple independent components: the first package, the intermediate structure with carrier substrate and RDLs, and the second package. This segmentation allows each component to be optimized independently, enabling reduced package thickness while maintaining adequate pitch between connection points through the distributed RDL architecture on the intermediate substrate.

Inventive Principle:
Principle #1Segmentation

3Productivity

If PoP technology is used to achieve denser integration, then integration density is improved, but total thickness reduction is limited by solder ball constraints

Engineering Contradiction:
Improveintegration densityVSAvoidtotal package thickness
Core Design Contradiction:
ProductivityVSLength of stationary object

Solution Approach 1:

The intermediate structure acts as a mediator that enables PoP technology to achieve both high integration density and reduced total thickness. By providing redistribution layers on an intermediate substrate, the patent allows multiple packages to be stacked with reduced individual package thicknesses, as the RDLs handle the electrical connectivity that would otherwise require thick solder ball joints, thereby enabling further total thickness reduction while maintaining dense integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11631611B2Wafer level chip scale packaging intermediate structure apparatus and method
Publication Date: 2023.04.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11631611B2 patent drawing
  • US11631611B2 patent drawing
  • US11631611B2 patent drawing

AI summary

Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.