Wafer Level Chip Scale Package Laser Marking Back Metal Integrity

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Solution Overview

Problem

Existing methods for laser marking wafer level chip scale packages with back metal, such as power MOSFETs, either damage the metal layer or lead to micro-chipping during dicing due to the sandwich structure, and are not cost-effective or suitable for thin wafers.

Innovation Solution

A method involving silicon etching, laser marking trenches on the backside surface of the wafer, followed by oxide etching and metal deposition to maintain a continuous back metal layer, ensuring undamaged and durable identification marks without affecting electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If direct laser marking is performed on the backside surface of MOSFET wafer, then durable identification marks are achieved, but the back metal layer is damaged and electrical resistance increases

Engineering Contradiction:

Improvedurability of identification markVSAvoidelectrical performance of chip

Core Design Contradiction:

Duration of action of stationary objectVSReliability

Solution Approach 1:

The laser marking is performed on the bare silicon wafer backside surface before the back metal layer is deposited. This preliminary action creates the durable identification mark on the silicon surface, and then the subsequent metal deposition process covers the marked surface, sealing the mark while maintaining metal continuity and avoiding damage to the back metal layer.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of marking the metal layer directly (which causes damage), the invention inverts the sequence by marking the silicon surface first, then covering it with metal. This reverse approach achieves durable marking without compromising the electrical integrity of the back metal layer.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If coating or film is applied to MOSFET backside surface for indirect marking, then electrical performance is maintained, but micro-chipping occurs during dicing due to sandwich structure

Engineering Contradiction:

Improveelectrical performance of chipVSAvoidstructural integrity during dicing

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The invention removes the problematic intermediate coating or film layer from the structure. By marking the bare silicon surface directly and then depositing a continuous metal layer, the sandwich structure (Si/metal/organic film) is eliminated, replacing it with a simpler Si/metal structure that does not suffer from micro-chipping during dicing.

Inventive Principle:

Principle #2Taking out (Extraction)

3Ease of manufacture

If coating or film is applied to MOSFET backside surface, then indirect marking is enabled, but manufacturing cost increases

Engineering Contradiction:

Improvefeasibility of indirect markingVSAvoidmanufacturing cost

Core Design Contradiction:

Ease of manufactureVSQuantity of substance

Solution Approach 1:

The invention eliminates the need for expensive intermediate coating or film materials by using the silicon surface itself for marking. The laser mark is created directly on the silicon, and the subsequently deposited metal layer serves as the protective and conductive layer, removing the need for additional organic film layers and reducing material costs.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides a durable and continuous back metal layer, reducing electrical resistance and preventing micro-chipping, while being cost-effective and suitable for thin wafers, ensuring reliable identification marks.

Implementation Method 1

laser marking the backside surface of the wafer following the silicon etch step

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

depositing a metal layer on the backside surface of the wafer following the oxide etch step

Methodology Applied

Scientific EffectMetal deposition: Deposition (physical)

Data Source

PatentUS7842543B2Wafer level chip scale package and method of laser marking the same

Publication Date: 2010.11.30 ALPHA & OMEGA SEMICONDUCTOR INC

AI summary

A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.