Wafer-Level Chip-Scale Package Plasma Passivation
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Solution Overview
Problem
The design and implementation of chip-scale packages face challenges due to limited space for electrical circuits within plastic packages, requiring smaller silicon dies and complex manufacturing processes, which affect electrical isolation, humidity protection, and solderability.
Innovation Solution
The development of self-contained chip-scale device packages with a silicon wafer connected to a printed circuit board (PCB) via conductive contacts and an interconnect structure, featuring an electrically isolating plasma coating on sidewalls and non-active sides to mitigate current leakage, allowing for smaller gaps and non-rectangular shapes, and using plasma dicing to facilitate efficient dicing and coating application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plastic packages are used for chip packaging, then electrical isolation and protection are improved, but the space available for electrical circuits is reduced
Solution Approach 1:
The package is divided into functional regions: the silicon die area for electrical circuits and the plastic package body for protection and isolation. This segmentation allows each region to be optimized for its specific function, with the die occupying minimal space while the package provides comprehensive protection.
Solution Approach 2:
The silicon die is nested within the plastic package body, with the die being significantly smaller than the package. This nesting arrangement allows the active circuit area to be maximized while the package structure provides the necessary protection and isolation without occupying excessive space.
2Reliability
If lead frame and wire loop are included in plastic packages, then electrical connection is improved, but the space for silicon die is reduced
Solution Approach 1:
The invention extracts and eliminates the traditional lead frame and wire loop structures from the package. Instead, electrical connections are achieved through alternative means such as substrate-mounted interconnects or direct die-to-PCB bonding, removing the space-consuming intermediate structures while maintaining electrical connectivity.
3Productivity
If dicing is performed to separate chip-scale packages, then individual device production is improved, but manufacturing complexity increases
Solution Approach 1:
The packages are pre-formed as complete units on the silicon wafer before dicing. All necessary components including the die, interconnects, and package structures are prepared in advance on the wafer, allowing for simple and efficient separation through dicing without requiring complex assembly operations after cutting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of chip-scale packages with improved electrical isolation, protection against humidity and mechanical damage, and efficient manufacturing, allowing for nearly full utilization of the device size for electrical circuits while maintaining high isolation and manufacturability.
Implementation Method 1
an electrically isolating coating, such as a plasma coating, that continuously extends along, and is in contact with, one of sidewalls and the non-active side
Data Source
AI summary
Aspects of the disclosure are directed towards an efficient wafer level chip-scale package, and methods or producing the packages. Various aspects are directed to protecting against humidity, contamination, mechanical damage, and current leakage while maintaining isolation and manufacturability of the plastic package and a ratio of active die size to package size.